參數(shù)資料
型號(hào): DAC7725U
元件分類(lèi): 外設(shè)及接口
英文描述: Single Supply RS232C Line Driver/Receiver(?????μ?o?RS232C ?o?????????¨???2???2??????)
中文描述: 單電源RS232C接口線(xiàn)路驅(qū)動(dòng)器/接收器(單電源RS232C接口線(xiàn)收發(fā)器(2發(fā)2收))
文件頁(yè)數(shù): 12/15頁(yè)
文件大?。?/td> 451K
代理商: DAC7725U
12
DAC7724, 7725
THEORY OF OPERATION
The DAC7724 and DAC7725 are quad voltage output,
12-bit digital-to-analog converters (DACs). The architecture
is a classic R-2R ladder configuration followed by an opera-
tional amplifier that serves as a buffer, as shown in Figure 1.
Each DAC has its own R-2R ladder network and output op-
amp, but all share the reference voltage inputs. The mini-
mum voltage output (“zero-scale”) and maximum voltage
output (“full-scale”) are set by the external voltage refer-
ences (V
REFL
and V
REFH
, respectively). The digital input is
a 12-bit parallel word and the DAC input registers offer a
readback capability. The converters can be powered from a
single +15V supply or a dual
±
15V supply. Each device
offers a reset function which immediately sets all DAC
registers and DAC output voltages to mid-scale (DAC7724,
code 800
H
) or to zero-scale (DAC7725, code 000
H
). See
Figures 2 and 3 for the basic operation of the DAC7724/25.
FIGURE 1. DAC7724/25 Architecture.
FIGURE 2. Basic Single-Supply Operation of the DAC7724/25.
R
2R
2R
2R
2R
2R
2R
2R
2R
2R
V
REF
H
V
OUT
R
R
R
R
R
R
V
REF
L
R
F
1
2
3
4
V
REFH
V
OUTB
Load DAC Registers
Reset DACs
(1)
V
OUTA
V
SS
5
GND
6
RESET
7
8
9
10
11
12
13
14
LDAC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
V
REFL
V
OUTC
DAC7724
DAC7725
V
OUTD
V
CC
28
27
26
25
V
DD
24
CS
23
A0
A1
R/W
DB11
DB10
DB9
DB8
DB7
22
21
20
19
18
17
16
15
Chip Select
Read/Write
Data Bus
Data Bus
Address Bus
or Decoder
+15V
NOTE: (1) Reset LOW sets all DACs to code 800
H
on the DAC7724 and to code 000
H
on the DAC7725.
0V to +10V
0V to +10V
0V to +10V
0V to +10V
0.1
μ
F
1
μ
F to 10
μ
F
+
+5V
0.1
μ
F
1
μ
F to 10
μ
F
+
+10.00V
0.1
μ
F
相關(guān)PDF資料
PDF描述
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