參數(shù)資料
型號: DAC7664YBR
廠商: Texas Instruments, Inc.
英文描述: 16-BIT, QUAD VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER
中文描述: 16位四路電壓輸出數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù): 23/28頁
文件大?。?/td> 452K
代理商: DAC7664YBR
SBAS271 MARCH 2004
www.ti.com
23
3V TO 5V LOGIC INTERFACE
All of the digital input and output pins are compatible with
any logic supply voltage between 3V and 5V. Connect the
interface logic supply voltage to the IOV
DD
pin. Note that
the internal digital logic operates from 5V, so the VDD pin
must connect to a 5V supply.
GLITCH SUPPRESSION CIRCUIT
Figure 21, Figure 22, Figure 48, and Figure 49 show the
typical DAC output when switching between codes 7FFFh
and 8000h. For R-2R ladder DACs, this is potentially the
worst-case glitch condition, since every switch in the DAC
changes state. To minimize the glitch energy at this and
other code pairs with possible high-glitch outputs, an
internal track-and-hold circuit is used to maintain the DAC
ouput voltage at a nearly constant level during the internal
switching interval. This track-and-hold circuit is activated
only when the transition is at, or close to, one of the code
pairs with the high-glitch possibility.
It is advisable to avoid digital transitions within 1
μ
s of the
rising edge of the LDAC signal. These signals can affect
the charge on the track-and-hold capacitor, thus
increasing the glitch energy.
DIGITAL TIMING
Figure 57 and Table 2 provide detailed timing information
for the digital interface of the DAC7664.
DIGITAL INPUT CODING
The DAC7664 input data is in straight binary format. The
output voltage for single-supply operation is given by
Equation 1:
V
OUT
2.5
65,536
N
where N is the digital input code.
This equation does not include the effects of offset
(zero-scale) or gain (full-scale) errors.
The output for the dual supply operation is given by
Equation 2:
V
OUT
5
65,536
N
2.5
(1)
(2)
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