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參數(shù)資料
| 型號(hào)： | DAC7644EB |
| 元件分類(lèi)： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 8 us SETTLING TIME, 16-BIT DAC, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁(yè)數(shù)： | 11/21頁(yè) |
| 文件大?。?/td> | 349K |
| 代理商： | DAC7644EB |
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DAC7644
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE
(LSB)
DLE
(LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25
°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H C000H
E000
H FFFFH
FIGURE 11. Linearity and Differential Linearity Error Curves
for Figure 10.
NC
V
OUTA Sense
V
OUTA
V
REFL AB Sense
V
REFL AB
V
REFH AB
V
REFH AB Sense
V
OUTB Sense
V
OUTB
48
47
46
45
44
43
42
41
40
39
38
37
DAC7644
+2.5V
+V
V
OUT
V
OUT
FIGURE 12. Low Cost Single-Supply Configuration.
FIGURE 13. Linearity and Differential Linearity Error Curves
for Figure 12.
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE
(LSB)
DLE
(LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25
°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H C000H
E000
H FFFFH
DIGITAL INTERFACE
Table I shows the basic control logic for the DAC7644. Note
that each internal register is edge triggered and not level
triggered. When the LOADDACS signal is transitioned to
HIGH, the digital word currently in the register is latched.
The first set of registers (the input registers) are triggered via
the A0, A1, R/W, and CS inputs. Only one of these registers
is transparent at any given time.
The double-buffered architecture is designed mainly so each
DAC input register can be written to at any time and then all
DAC voltages updated simultaneously by the rising edge of
LOADDACS. It also allows a DAC input register to be
written to at any point and the DAC voltages to be synchro-
nously changed via a trigger signal connected to
LOADDACS.
INPUT
DAC
A1
A0
R/W
CS
RST
RSTSEL LOADDACS
REGISTER
MODE
DAC
LLLL
H
X
Write
Hold
Write Input
A
L
H
L
H
X
Write
Hold
Write Input
B
H
L
H
X
Write
Hold
Write Input
C
H
L
H
X
Write
Hold
Write Input
D
L
H
L
H
X
Read
Hold
Read Input
A
L
H
L
H
X
Read
Hold
Read Input
B
H
L
H
L
H
X
Read
Hold
Read Input
C
H
L
H
X
Read
Hold
Read Input
D
XXX
H
X
↑
Hold
Write
Update
All
X
H
X
H
Hold
All
XXXX
↑
L
X
Reset to Zero
All
XXXX
↑
H
X
Reset to Midscale
All
TABLE I. DAC7644 Logic Truth Table.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC7644EB | 制造商:Texas Instruments 功能描述:IC 16BIT DAC 100KHZ SSOP48 制造商:Texas Instruments 功能描述:IC, 16BIT DAC, 100KHZ, SSOP48 制造商:Texas Instruments 功能描述:IC, 16BIT DAC, 100KHZ, SSOP48; Resolution (Bits):16bit; Sampling Rate:100kSPS; Input Channel Type:Parallel; Supply Voltage Range: 4.75V to 5.25V; Digital IC Case Style:SSOP; No. of Pins:48; Data Interface:Parallel; Supply ;RoHS Compliant: Yes |
| DAC7644EB/1K | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 16-Bit Quad Voltage Output RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC7644EB/1KG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 16-Bit Quad Voltage Output RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC7644EBG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 16-Bit Quad Voltage Output RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC7644EG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 16-Bit Quad Voltage Output RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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