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參數(shù)資料
| 型號： | DAC7632VFT |
| 英文描述： | RIBBON CABLE, 26WAY, PER M; Cores, No. of:26; Conductor make-up:7/36AWG; Wire size, AWG:28AWG; Impedance:119R; Pitch:1.27mm; Voltage rating, AC:50V; Colour:Grey; Capacitance:70.5pF/m; Approval Bodies:UL; Approval category:Style RoHS Compliant: Yes |
| 中文描述： | 16位，雙電壓輸出數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 17/21頁 |
| 文件大?。?/td> | 846K |
| 代理商： | DAC7632VFT |
DAC7632
SBAS234
17
www.ti.com
INPUT
REGISTER
DAC
DACSEL
CS
RST
RSTSEL
LDAC
LOAD
REGISTER
MODE
DAC
0
1
X
X
X
X
L
L
H
H
X
X
H
H
H
H
↑
↑
X
X
X
X
L
H
X
X
↑
H
X
X
L
L
H
H
X
X
Write
Write
Hold
Hold
Hold
Hold
Write
Hold
Write Input
Write Input
Update
Hold
Reset to Zero-Scale
Reset to Mid-scale
A
B
All
All
All
All
Reset to 0000
H
Reset to 8000
H
Reset to 0000
H
Reset to 8000
H
TABLE I. DAC7632 Logic Truth Table.
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
DACSEL
X
X
X
X
X
X
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
QUICK
LOAD
SERIAL DATA INPUT
CS
(1)
CLK
(1)
LOAD
RST
SERIAL SHIFT REGISTER
H
(2)
X
(3)
H
H
No Change
L
(4)
L
H
H
No Change
L
↑
↑
(5)
L
H
H
Advanced One Bit
H
H
Advanced One Bit
H
(6)
X
L
(7)
H
No Change
H
(6)
X
H
↑
(8)
No Change
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH.
(3) X = Don
’
t Care. (4) L = Logic LOW. (5) = Positive Logic Transition.
(6) A HIGH value is suggested in order to avoid a
“
false clock
”
from
advancing the shift register and changing the shift register. (7) If data is
clocked into the serial register while LOAD is LOW, the input registers will
change as data flows through the shift register. This will corrupt the data
in each DAC register that has been erroneously selected. (8) Rising edge
of RST causes no change in the contents of the serial shift register.
TABLE II. Serial Shift Register Truth Table.
FIGURE 14. Daisy-Chaining Multiple DAC7632s.
DAC7632
CLK
SDI
CS
SCK
DIN
CS
SDO
DAC7632
CLK
SDI
CS
SDO
DAC7632
CLK
SDI
CS
SDO
To
Other
Serial
Devices
Data presented to SDI is clocked into the shift register on
each rising CLK edge. This data is latched into the input
register(s) via a logic-low level on
LOAD
. The data is directed
from the shift register to the desired input register(s) specified
by data bits 21 and 23. The internal DAC registers are edge
triggered and not level triggered. When the LDAC signal is
transitioned from LOW to HIGH, the digital word currently in
the input registers are latched. This double-buffered architec-
ture has been designed so that new data can be entered for
each DAC without disturbing the analog outputs. When the
new data has been entered into the device, both DAC
outputs can be updated simultaneously by the rising edge of
LDAC. Additionally, it allows the input registers to be written
to at any point, then the DAC output voltages can be
synchronously changed via a trigger signal (LDAC).
Note that
CS
and CLK are combined with an OR gate, which
controls the serial-to-parallel shift register. These two inputs
are completely interchangeable. In addition, care must be
taken with the state of CLK when
CS
rises at the end of a
serial transfer. If CLK is LOW when
CS
rises, the OR gate
will provide a rising edge to the shift register, shifting the
internal data one additional bit. The result will be incorrect
data and possible selection of the wrong input register(s). If
both
CS
and CLK are used,
CS
should rise only when CLK
is HIGH. If not, then either
CS
or CLK can be used to operate
the shift register (the remaining pin should be tied to DGND).
Please refer to Table II for more information.
SERIAL-DATA OUTPUT
The Serial-Data Output pin (SDO) is the internal shift register
’
s
output. For the DAC7632, SDO is a driven output and does
not require an external pull-up. Any number of DAC7632s
can be daisy-chained by connecting the SDO pin of one
device to the SDI pin of the following device in the chain, as
shown in Figure 14.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DAC7654 | Label; Features:Face paper: 56#gloss coated; Tensile: 30lbf/in.; Adhesive: strong, permanent: Liner: 40# white kraft; Service temp: -4 to ??? deg. F; Min labeling temp: deg. F; Height:4"; Width:4" RoHS Compliant: NA |
| DAC7654YBR | TAPE, ADHESIVE, ALUMINIUM, 19MM; Length, tape:3.66m; Width, tape:19mm RoHS Compliant: Yes |
| DAC7654YBT | 3.2 Mil Aluminum Foil Conductive Acrylic on Liner 1 inch x 18 yd RoHS Compliant: Yes |
| DAC7654YCR | EMI ALUMINUM FOIL SHIELDING TAPE, 1 IN. X 18 YD |
| DAC7654YCT | TAPE, ADHESIVE, COPPER, 19MM; Length, tape:3.66m; Width, tape:19mm RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC7632VFT | 制造商:Texas Instruments 功能描述:IC 16BIT DAC SMD 7632 LQFP32 |
| DAC7632VFTG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 16-Bit Dual Vltg Out w/Serial Interface RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC7634 | 制造商:BB 制造商全稱:BB 功能描述:16-BIT, QUAD VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER |
| DAC7634E | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 16-Bit Quad Voltage Output RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC7634E | 制造商:BURR-BROWN 功能描述:IC 16BIT DAC SMD 7634 SSOP48 制造商:Texas Instruments 功能描述:Digital-Analog Converter IC Interface Ty |
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