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參數(shù)資料
| 型號： | DAC7615PB |
| 元件分類： | 外設及接口 |
| 英文描述： | Single Supply RS232C Line Driver/Receiver(?????μ?o?RS232C ?o?????????¨???2???2??????) |
| 中文描述： | 單電源RS232C接口線路驅動器/接收器（單電源RS232C接口線收發(fā)器（2發(fā)2收）） |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 485K |
| 代理商： | DAC7615PB |
10
DAC7615
REFERENCE INPUTS
The reference inputs, V
REFL
and V
REFH
, can be any voltage
between V
SS
+ 2.25V and V
DD
– 2.25V provided that V
REFH
is at least 1.25V greater than V
REFL
. The minimum output
of each DAC is equal to V
REFL
– 1LSB plus a small offset
voltage (essentially, the offset of the output op amp). The
maximum output is equal to V
REFH
plus a similar offset
voltage. Note that V
SS
(the negative power supply) must
either be connected to ground or must be in the range of –
4.75V to –5.25V. The voltage on V
SS
sets several bias
points within the converter. If V
SS
is not in one of these two
configurations, the bias values may be in error and proper
operation of the device is not guaranteed.
The current into the reference inputs depends on the DAC
output voltages and can vary from a few microamps to
approximately 0.6 milliamp. Bypassing the reference volt-
age or voltages with a 0.1
μ
F capacitor placed as close as
possible to the DAC7615 package is strongly recommended.
DIGITAL INTERFACE
Figure 3 and Table I provide the basic timing for the
DAC7615. The interface consists of a serial clock (CLK),
serial data (SDI), a load register signal (LOADREG), and a
“l(fā)oad all DAC registers” signal (LOADDACS). In addition,
a chip select (CS) input is available to enable serial commu-
nication when there are multiple serial devices. An asyn-
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
DS
t
DH
t
CH
t
CL
t
CSS
t
CSH
t
LD1
t
LD2
t
LDRW
t
LDDW
t
RSSH
t
RSTW
t
S
Data Valid to CLK Rising
25
ns
Data Held Valid after CLK Rises
20
ns
CLK HIGH
30
ns
CLK LOW
50
ns
CS LOW to CLK Rising
55
ns
CLK HIGH to CS Rising
15
ns
LOADREG HIGH to CLK Rising
40
ns
CLK Rising to LOADREG LOW
15
ns
LOADREG LOW Time
45
ns
LOADDACS LOW Time
45
ns
RESETSEL Valid to RESET LOW
25
ns
RESET LOW Time
Settling Time
70
10
ns
μ
s
FIGURE 3. DAC7615 Timing.
chronous reset input (RESET) is provided to simplify start-
up conditions, periodic resets, or emergency resets to a
known state.
The DAC code and address are provided via a 16-bit serial
interface as shown in Figure 3. The first two bits select the
input register that will be updated when LOADREG goes
LOW (see Table II). The next two bits are not used. The last
12 bits are the DAC code which is provided, most significant
bit first.
TABLE I. Timing Specifications (T
A
= –40
°
C to +85
°
C).
A1
(MSB)
(LSB)
SDI
CLK
CS
LOADREG
A0
X
X
D11
D10
D9
D3
D2
D1
D0
SDI
CLK
LOADDACS
RESET
V
OUT
tcss
t
LD1
t
CL
t
CH
t
DS
t
DH
t
LD2
t
LDRW
t
LDDW
t
S
t
RSTW
t
RSSH
t
CSH
t
S
1 LSB
ERROR BAND
1 LSB
ERROR BAND
RESETSEL
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