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參數(shù)資料
| 型號： | DAC7552IRGT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 12-BIT, DUAL, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 12位雙，超低毛刺，電壓輸出數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 862K |
| 代理商： | DAC7552IRGT |
www.ti.com
TIMING CHARACTERISTICS
(1)(2)
V
DD
= 2.7 V to 5.5 V, R
L
= 2 k
to GND; all specifications –40°C to 105°C, unless otherwise specified
SCLK
SYNC
SDIN
D15
D14
D13
D12
D11
D1
D0
D15
t
8
t
4
t
3
t
2
t
1
t
7
t
6
t
5
D0
t
9
Input Word n
Input Word n+1
Undefined
D15
D14
D0
Input Word n
t
10
SDO
CLR
DAC7552
SLAS442B–JANUARY 2005–REVISED JUNE 2005
PARAMETER
TEST CONDITIONS
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
MIN
20
20
10
10
10
10
TYP
MAX
UNITS
t
1(3)
SCLK cycle time
ns
t
2
SCLK HIGH time
ns
t
3
SCLK LOW time
ns
4
4
5
5
SYNC falling edge to SCLK falling edge setup
time
t
4
ns
t
5
Data setup time
ns
4.5
4.5
t
6
Data hold time
ns
0
0
t
7
SCLK falling edge to SYNC rising edge
ns
20
20
10
10
10
10
t
8
Minimum SYNC HIGH time
ns
t
9
SCLK falling edge to SDO valid
ns
t
10
CLR pulse width low
ns
(1)
(2)
(3)
All input signals are specified with t
= t
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
See Serial Write Operation timing diagram
Figure 1
.
Maximum SCLK frequency is 50 MHz at V
DD
= 2.7 V to 5.5 V.
Figure 1. Serial Write Operation
5
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