
DAC7528
4
ELECTROSTATIC
DISCHARGE SENSITIVITY
Any integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND ................................................................................. 0V, +7V
V
REFA, B
to GND ................................................................................
±
25V
R
to GND ...................................................................................
±
25V
Digital Input Voltage Range................................................ –0.3V to V
DD
Output Voltage (pins 2, 20) ................................................ –0.3V to V
DD
Operating Temperature Range U,P ................................–40
°
C to +85
°
C
DICE ............................... 0
°
C to +70
°
C
Junction Temperature .................................................................. +150
°
C
Storage Temperature.....................................................–60
°
C to +150
°
C
Lead Temperature (soldering, 10s) ............................................. +300
°
C
θ
JA
U package ........................................................................105
°
C/W
P package........................................................................... 85
°
C/W
θ
JC
U package ......................................................................... 60
°
C/W
P package.......................................................................... 35
°
C/W
NOTES:
θ
JA
is specified for worst case mounting conditions, i.e.,
θ
JA
is
specified for device in socket for PDIP package.
CAUTION: (1) Do not apply voltages higher than V
or less than GND
potential on any terminal except V
(pins 4 and 18) and R
(pins
3 and 19). (2) The digital control inputs are zener-protected: however,
permanent damage may occur on unprotected units from high-energy
electrostatic fields. Keep units in conductive foam at all times until ready
to use. (3) Use proper antistatic handling procedures. (4) Absolute
Maximum Ratings apply to both packaged devices and DICE. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device.
TYPICAL PERFORMANCE CURVES
At V
DD
= +5V; V
REFA,B
= +10V; I
OUT
= GND = 0V: T = Full Temperature Range Specification under Absolute Maximum Ratings unless otherwise noted.
WRITE CYCLE TIMING DIAGRAM
t
DS
V
IH
V
IL
Data
In Stable
V
DD
0
t
WR
t
AS
t
AH
V
DD
0
V
DD
0
Data In
(DB0-DB7)
WR
DAC A/DAC B
t
CS
t
CH
V
DD
0
CS
t
DH
NOTE: All input signal rise and fall times are measured from 10% to 90%
of V
. V
= +5V, t
= t
= 20ns; V
= +15V, t
r
= t
f
= 40ns. Timing
measurement reference level is (V
IH
+ V
IL
)/2.
Digital Inputs:
All digital inputs of the DAC7528 incorpo-
rate on-chip ESD protection circuitry. This protection is
designed and has been tested to withstand five 2500V
positive and negative discharges (100pF in series with 1500
)
applied to each digital input.
Analog Pins:
Each analog pin has been tested to Burr-
Brown's analog ESD test consisting of five 1000V positive
and negative discharges (100pF in series with 1500
) ap-
plied to each pin. R
FB A
, V
REF A
, R
FB B
, and V
REF B
show
some sensitivity.
MODE SELECTION TABLE
DAC A/DAC B
CS
WR
DAC A
DAC B
L
H
X
X
L
L
H
X
L
L
X
H
WRITE
HOLD
HOLD
HOLD
HOLD
WRITE
HOLD
HOLD
SUPPLY CURRENT vs DIGITAL INPUT VOLTAGE
0
1.0
2.0
3.0
4.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
V
DD
= +5V
V
IN
(V)
I
D
5
DAC7528 GAIN TC
4
3
2
1
0
–1
–2
–3
–4
–5
–40
–20
0
20
40
60
80
100
Temperature (°C)
G