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參數(shù)資料
| 型號(hào)： | DAC729 |
| 英文描述： | DAC729 - DISCONTINUED PRODUCT. No longer recommended for new design. |
| 中文描述： | DAC729 -已停產(chǎn)產(chǎn)品。不再推薦用于新設(shè)計(jì)。 |
| 文件頁(yè)數(shù)： | 12/12頁(yè) |
| 文件大?。?/td> | 251K |
| 代理商： | DAC729 |
DAC729
12
the potentiometers in Figure 12 with V
OUT
DACs, and using
sample and difference measurements, the major carry bit
weights can be measured, and external DACs used to adjust
the differential linearity of the DAC729. A successive ap-
proximation routine yields the fastest calibration. The output
voltage of the external DACs will have to be level shifted,
as the bit adjustment potentiometer must be able to achieve
–V
CC
to give the full adjust range.
Because the DAC729 feedback resistors have a tolerance of
±
0.1%, the output range can be rescaled slightly with small-
value fixed external resistors to give convenient ranges. A
popular range is 0V to +10.24V which gives even 5mV steps
at 11 bits. In this case, the LSB size is 39.06
μ
V. Figure 14
shows how to connect two 240
resistors in series with the
internal 10k
resistors to give a 0V to 10.24V full-scale
range. Another convenient range might be 0V to +10.48576V
which gives an even 40
μ
V LSB step size.
THE HEART OF AN 18-BIT ADC
The DAC729 makes a good building block in ADC applica-
tions. The key to ADC accuracy is differential linearity of
the DAC. The ability to adjust to 18-bit linearity, coupled
with the fast settling time of the DAC729 makes the design
cycle for an 18-bit successive approximation ADC much
faster, and the production more consistent. Figure 15 shows
the DAC as the heart of a successive approximation ADC.
The clock and successive approximation register could be
implemented in 7400 series TTL, as a simple gate-array or
standard cell, or part of a local processor.
With the DAC out of the way, the comparator is the toughest
part of the ADC design. To resolve an 18-bit LSB, and
interface to a TTL-logic device, the comparator must have a
gain of 500kV/V (5
X
actual) as well as low hysteresis, low
noise, and low thermally induced offsets. With this much
gain, a slow comparator may be desired to reduce the risk of
instability.
FIGURE 15. Block Diagram of an 18-Bit Resolution
±
10V
IN
ADC.
FIGURE 14. 0V to 10.24V Using Internal Op Amp and
Internal Reference.
OPA602
10M
To Holy
Point Ground
OPA633
10k
10k
Ref In
Ref Out
Clock
SAR
≈
2k
Custom Design
Comparator
DAC729
18-Bits
The feedback resistors of the DAC are the input scaling
resistors of the ADC. An OPA602 and an OPA633 make an
excellent buffer for the input signal, giving a very high input
impedance to the signal (minimizing IR drop) while main-
taining the linearity.
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1
1
18-Bit
DAC
0 to 10.24V
240
240
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