
4
DAC712
ABSOLUTE MAXIMUM RATINGS
+V
CC
to COMMON ...................................................................... 0V, +17V
–V
CC
to COMMON ...................................................................... 0V, –17V
+V
CC
to –V
CC
........................................................................................ 34V
Digital Inputs to COMMON .......................................... –1V to +V
–0.7V
External Voltage Applied to BPO and Range Resistors.....................
±
V
CC
V
REF OUT
...................................................... Indefinite Short to COMMON
V
OUT
Power Dissipation .......................................................................... 750mW
Storage Temperature ...................................................... –60
°
C to +150
°
C
Lead Temperature (soldering, 10s)................................................ +300
°
C
NOTE: Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE DRAWING
NUMBER
(1)
PRODUCT
PACKAGE
DAC712P
DAC712U
DAC712PB
DAC712UB
DAC712PK
DAC712UK
DAC712PL
DAC712UL
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
246
217
246
217
246
217
246
217
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
PACKAGE INFORMATION
TIMING DIAGRAM
TIMING SPECIFICATIONS
T
A
= –40
°
C to +85
°
C, +V
CC
= +12V or +15V, –V
CC
= –12V or –15V.
SYMBOL
PARAMETER
MIN
MAX
UNITS
t
DW
t
AW
t
AH
t
DH
t
WP(1)
t
CP
Data Valid to End of WR
A
0
, A
1
Valid to End of WR
A
, A
Hold after End of WR
Data Hold after end of WR
Write Pulse Width
CLEAR Pulse Width
50
50
10
10
50
200
ns
ns
ns
ns
ns
ns
NOTES: (1) For single-buffered operation, t
WP
is 80ns min. Refer to page 10.
WR
A
0
, A
1
D0-D15
t
DH
t
AW
t
WP
t
DW
t
AH
A
0
0
1
1
0
X
X
A
1
1
0
1
0
X
X
WR
CLR
DESCRIPTION
1
→
0
→
1
1
→
0
→
1
1
→
0
→
1
0
1
X
1
1
1
1
1
0
Load Input Latch
Load D/A Latch
No Change
Latches Transparent
No Change
Reset D/A Latch
TRUTH TABLE
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-Brown
Corporation recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published speci-
fications.
ORDERING INFORMATION
LINEARITY
ERROR MAX
at +25
°
C
DIFFERENTIAL
LINEARITY ERROR
MAX at +25
°
C
TEMPERATURE
RANGE
PRODUCT
DAC712P
DAC712U
DAC712PB
DAC712UB
DAC712PK
DAC712UK
DAC712PL
DAC712UL
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
±
4LSB
±
4LSB
±
2LSB
±
2LSB
±
2LSB
±
2LSB
±
2LSB
±
2LSB
±
4LSB
±
4LSB
±
2LSB
±
2LSB
±
2LSB
±
2LSB
±
1LSB
±
1LSB