- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄376558 > DAC488HR (Electronic Theatre Controls, Inc.) 16-bit D/A Converter with Digital I/O & IEEE 488 PDF資料下載
參數(shù)資料
| 型號(hào)： | DAC488HR |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16-bit D/A Converter with Digital I/O & IEEE 488 |
| 中文描述： | 16位D / A的數(shù)字I /轉(zhuǎn)換器? |
| 文件頁(yè)數(shù)： | 2/4頁(yè) |
| 文件大?。?/td> | 190K |
| 代理商： | DAC488HR |
249
Q U I C K F I N D
the smart approach to instrumentation
I
tel: 440-439-4091
fax: 440-439-4093
sales@iotech.com
www.iotech.com
DAC488HR
General Information
DAC488HR Design
Four independent analog output modules are optically isolated
from the IEEE 488 bus, digital circuitry, earth ground, and
chassis common by up to 500 VDC. Each module consists of a
microcontroller and expandable data buffer. A common update
clock is shared by all ports, ensuring synchronization. Four
internal clock sources are available to meet a wide variety of
applications including CD and DAT testing. An external clock
source (up to 10 MHz) allows synchronization to an external
frequency reference and can be used to synchronize the
DAC488HR to the ADC488A series (see p. 243) digitizers for
stimulus/response applications.
Multiple Trigger Sources
All DAC488HR ports share a common trigger source, ensuring
multi-channel synchronization for applications with critical
time and phase relationships. Trigger sources for the DAC488HR
include trigger command, IEEE 488 Group Execute Trigger
(GET), and external TTL (rising or falling edge) signal input.
Triggers can also be initiated on periodic intervals from 2 ms to
65,535 ms, specified in 1 ms increments. The DAC488HR pro-
vides a delayed TTL-level trigger output for stimulus/response
applications in which the device under test (DUT) must attain a
steady state prior to measurement. This function allows users to
specify a time delay, in update clock counts from 1 to 65,535,
between the DAC488HR’s output and the trigger signal’s output.
Multiple Clock Sources
The DAC488HR features four internal clock sources and accommo-
dates an external clock source (up to 10 MHz) for updating the
output ports. A 16-bit counter is used to provide update rates to
meet application requirements. For example, the 200-kHz clock
and the 5-MHz clock can be divided down to any rate between 3 Hz
and 100 kHz for general purpose applications; the
5.6448-MHz clock can simulate 44.1-kHz audio CD signals; and the
6.144-MHz can simulate 48-kHz audio DAT signals. For synchro-
nizing external circuitry to DAC488HR output, an update clock
signal is also provided.
Buffer Management
The DAC488HR’s step, burst, waveform, and continuous trigger
output modes can be used with flexible buffer management
functions to output stepped voltages, any one of five standard
waveforms, or user-defined arbitrary waveforms. Waveforms are
loaded from the IEEE 488 bus into the DAC488HR’s resident
8 Ksample buffer at rates up to 500 Kbytes/s.
To output standard predefined sine, square, and triangle wave-
forms, the user specifies the starting memory location, number
of samples, max/min values, duty cycle, and the number of
times the cycle is to be repeated or “l(fā)ooped.” The “l(fā)ooping”
function outputs specified buffer segments up to the full avail-
able buffered size for repetition up to 65,535 times. This con-
serves memory space by allowing long periodic waveforms to be
defined in a single cycle. Additionally, for applications that
exceed the DAC488HR’s internal buffer capacity, waveforms
can be output continuously from an IEEE 488 controller at up to
200 Kbytes/s via the IEEE 488 bus.
Nonvolatile Storage
The DAC488HR uses resident nonvolatile random access
memory (NVRAM) to store the calibration constants deter-
mined during digital calibration, and to store its power-up
default configuration.
Each DAC488HR output port features a separate microprocessor and
buffer memory for independent waveform management
D/A
channel 3
D/A
channel 1
Isolated
analog
output
Non-isolated
digital I/O
IEEE 488
interface
Internal
peripheral
interface
bus
D/A
channel 2
D/A
channel 4
Non-
isolated
Isolated
Power
source 1
Power
source 2
Power
source 3
Power
source 4
PS
main
Main
processor
digital
circuitry
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DAC4C | Converter IC |
| DAC4E | Converter IC |
| DAC5573IWR | QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, INTERFACE DIGITAL-TO-ANALOG CONVERTER |
| DAC5574EVM | DAC5574 Evaluation Module(DAC5574評(píng)估模塊) |
| DAC6574EVM | DAC6574 Evaluation Module(DAC6574評(píng)估模塊) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC488HR/2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-bit D/A Converter with Digital I/O & IEEE 488 |
| DAC488HR/4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-bit D/A Converter with Digital I/O & IEEE 488 |
| DAC4C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
| DAC-4-CG | 制造商:Thomas & Betts 功能描述:Universal Recessed Box And Cover |
| DAC4E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。