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參數(shù)資料
| 型號： | DAC4814 |
| 英文描述： | Quad 12-Bit Digital-to-Analog Converter Serial Interface |
| 中文描述： | 四路12位數(shù)字到模擬轉換器串行接口 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 235K |
| 代理商： | DAC4814 |
9
DAC4814
DISCUSSION OF
SPECIFICATIONS
INPUT CODES
All digital inputs of the DAC4814 are TTL and 5V CMOS
compatible. Input codes for the DAC4814 are either USB
(Unipolar Straight Binary) or BOB (Bipolar Offset Binary)
depending on the mode of operation. See Figure 3 for
±
10V
bipolar connection. See Figures 4 and 5 for 0 to 10V and 0
to –10V unipolar connections.
UNIPOLAR AND BIPOLAR
OUTPUTS FOR SELECTED INPUT
DIGITAL INPUT
UNIPOLAR (USB)
BIPOLAR (BOB)
FFF
HEX
800
HEX
7FF
HEX
000
HEX
+Full scale
+1/2 Full scale
+1/2 Full scale – 1 LSB
Zero
+Full scale
Zero
Zero – 1 LSB
–Full scale
INTEGRAL OR RELATIVE LINEARITY
This term, also known as end point linearity, describes the
transfer function of analog output to digital input code.
Integral linearity error is the deviation of the analog output
versus code transfer function from a straight line drawn
through the end points.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the deviation from an ideal 1
LSB change in the output voltage when the input code
changes by 1 LSB. A differential nonlinearity specification
of
±
1 LSB maximum guarantees monotonicity.
UNIPOLAR OFFSET ERROR
The output voltage for code 000
HEX
when the DAC is in
unipolar mode of operation.
BIPOLAR ZERO ERROR
The output voltage for code 800
HEX
when the DAC is in the
bipolar mode of operation.
GAIN ERROR
The deviation of the output voltage span (V
MAX
– V
MIN
)
from the ideal span of 10V – 1 LSB (unipolar mode) or 20V
– 1 LSB (bipolar mode). The gain error is specified with and
without the internal +10V reference error included.
OUTPUT SETTLING TIME
The time required for the output voltage to settle within a
percentage-of-full-scale error band for a full scale transition.
Settling to
±
0.012% (1/2 LSB) is specified for the DAC4814.
DIGITAL-TO-ANALOG GLITCH
Ideally, the DAC output would make a clean step change in
response to an input code change. In reality, glitches occur
during the transition. See Typical Performance Curves.
DIGITAL CROSSTALK
Digital crosstalk is the glitch impulse measured at the output
of one DAC due to a full scale transition on the other
DAC—see Typical Performance Curves. It is dominated by
digital coupling. Also, the integrated area of the glitch pulse
is specified in nV–s. See table of electrical specifications.
DIGITAL FEEDTHROUGH
Digital feedthrough is the noise at a DAC output due to
activity on the digital inputs—see Typical Performance
Curves.
OPERATION
DACs can be updated simultaneously or independently as
required. Data are transferred on falling clock edges into a
48-bit shift register. DAC D MSB is loaded first. Data are
transferred to the DAC registers when the LATCH signals
are brought low. The data are latched when the LATCH
signals are brought high. All LATCH signals may be tied
together to allow simultaneous update of the DACs if re-
quired. The output of the DAC shift register is provided to
allow cascading of several DACS on the same bit stream. By
using separate signals for LATCH A , LATCH B,
LATCH C, and LATCH D it is possible to update one of the
four DACs every 12 clock cycles.
When CLR is brought low, the input shift registers are
cleared to 000
HEX
while the DAC registers = 800
HEX
. If
LATCH is brought low after CLR, the DACs are updated
with 000
HEX
resulting in –10V (bipolar) or 0V (unipolar) on
the output.
CIRCUIT DESCRIPTION
Each of the four DACs in the DAC4814 consists of a CMOS
logic section, a CMOS DAC cell, and an output amplifier.
One buried-zener +10.0V reference and a reference inverter
(for a –10.0V reference) are shared by all DACs.
Figure 1 is a simplified circuit for a DAC cell. An R, 2R
ladder network is driven by a voltage reference at V
REF
.
Current from the ladder is switched either to I
OUT
or AGND
by 12 single-pole double-throw CMOS switches. This main-
tains constant current in each leg of the ladder regardless of
digital input code. This makes the resistance at V
REF
con-
stant (it can be driven by either a voltage or current refer-
ence). The reference can be either positive or negative
polarity with a range of up to
±
10V.
FIGURE 1. Simplified Circuit Diagram of DAC Cell.
D11
(MSB)
D10
D9
D0
(LSB)
AGND
I
R
R
R
2R
2R
2R
2R
2R
R
OUT
V
REF
R
FB
相關PDF資料 |
PDF描述 |
|---|---|
| DAC4814AP | Quad 12-Bit Digital-to-Analog Converter Serial Interface |
| DAC4814BP | Quad 12-Bit Digital-to-Analog Converter Serial Interface |
| DAC4815 | Quad 12-Bit Digital-to-Analog Converter 8-Bit Port Interface |
| DAC4815AP | Quad 12-Bit Digital-to-Analog Converter 8-Bit Port Interface |
| DAC4815BP | Quad 12-Bit Digital-to-Analog Converter 8-Bit Port Interface |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DAC4814AP | 制造商:BB 制造商全稱:BB 功能描述:Quad 12-Bit Digital-to-Analog Converter Serial Interface |
| DAC4814BP | 制造商:BB 制造商全稱:BB 功能描述:Quad 12-Bit Digital-to-Analog Converter Serial Interface |
| DAC4815 | 制造商:BB 制造商全稱:BB 功能描述:Quad 12-Bit Digital-to-Analog Converter 8-Bit Port Interface |
| DAC4815AP | 制造商:BB 制造商全稱:BB 功能描述:Quad 12-Bit Digital-to-Analog Converter 8-Bit Port Interface |
| DAC4815BP | 制造商:BB 制造商全稱:BB 功能描述:Quad 12-Bit Digital-to-Analog Converter 8-Bit Port Interface |
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