- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8985 > DAC312HPZ (Analog Devices Inc)IC DAC 12BIT HS MULT 20-DIP PDF資料下載
參數(shù)資料
| 型號： | DAC312HPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT HS MULT 20-DIP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 18 |
| 設置時間： | 250ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 375mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 786 (CN2011-ZH PDF) |
DAC312
–11–
REV. C
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided
where IO + IO = IFR. Current appears at the true output when a
“1” is applied to each logic input. As the binary count increases,
the sink current at pin 18 increases proportionally, in the fash-
ion of a “positive logic” D/A converter. When a “0” is applied to
any input bit, that current is turned off at pin 18 and turned on
at pin 19. A decreasing logic count increases IO as in a negative
or inverted logic D/A converter. Both outputs may be used si-
multaneously. If one of the outputs is not required it must still
be connected to ground or to a point capable of sourcing IFR; do
not leave an unused output pin open.
Both outputs have an extremely wide voltage compliance en-
abling fast direct current-to-voltage conversion through a resis-
tor tied to ground or other voltage source. Positive compliance
is 25 V above V– and is independent of the positive supply.
Negative compliance is +10 V above V–.
The dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. This fea-
ture is especially useful in cable driving, CRT deflection and in
other balanced applications such as driving center-tapped coils
and transformers.
POWER SUPPLIES
The DAC312 operates over a wide range of power supply volt-
ages from a total supply of 20 V to 36 V. When operating with
V– supplies of –10 V or less, IREF ≤ 1 mA is recommended. Low
reference current operation decreases power consumption and
increases negative compliance, reference amplifier negative
common-mode range, negative logic input range, and negative
logic threshold range; consult the various figures for guidance.
For example, operation at –9 V with IREF = 1 mA is not recom-
mended because negative output compliance would be reduced
to near zero. Operation from lower supplies is possible, however
at least 8 V total must be applied to insure turn-on of the inter-
nal bias network.
Symmetrical supplies are not required, as the DAC312 is quite
insensitive to variations in supply voltage. Battery operation is
feasible as no ground connection is required; however, an artifi-
cial ground may be used to insure logic swings, etc. remain be-
tween acceptable limits.
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the
DAC312 are guaranteed to apply over the entire rated operating
temperature range. Full-scale output current drift is tight, typi-
cally
±10 ppm/°C, with zero-scale output current and drift es-
sentially negligible compared to 1/2 LSB.
The temperature coefficient of the reference resistor R14 should
match and track that of the output resistor for minimum overall
full-scale drift. Settling times of the DAC312 decrease approxi-
mately 10% at –55
°C; at +125°C an increase of about 15% is
typical.
SETTLING TIME
The DAC312 is capable of extremely fast settling times; typi-
cally 250 ns at IREF = 1.0 mA. Judicious circuit design and care-
ful board layout must be employed to obtain full performance
potential during testing and application. The logic switch design
enables propagation delays of only 25 ns for each of the 12 bits.
Settling time to within 1/2 LSB of the LSB is therefore 25 ns,
with each progressively larger bit taking successively longer. The
MSB settles in 250 ns, thus determining the overall settling time
of 250 ns. Settling to 10-bit accuracy requires about 90 ns to
130 ns. The output capacitance of the DAC312 including the
package is approximately 20 pF; therefore, the output RC time
constant dominates settling time if RL > 500
.
Settling time and propagation delay are relatively insensitive to
logic input amplitude and rise and fall times, due to the high
gain of the logic switches. Settling time also remains essentially
constant for IREF values down to 0.5 mA, with gradual increases
for lower IREF values lies in the ability to attain a given output
level with lower load resistors, thus reducing the output RC
time constant.
Measurement of the settling time requires the ability to accu-
rately resolve
±1/2 LSB of current, which is ±500 nA for 4 mA
FSR. In order to assure the measurement is of the actual settling
time and not the RC time of the output network, the resistive
termination on the output of the DAC must be 500
or less.
This does, however, place certain limitations on the testing ap-
paratus. At IREF values of less than 0.5 mA, it is difficult to pre-
vent RC damping of the output and maintain adequate
sensitivity. Because the DAC312 has 8 equal current sources for
the 3 most significant bits, the major carry occurs at the code
change of 000111111111 to 111000000000. The worst case set-
tling time occurs at the zero to full-scale transition and it re-
quires 9.2 time constants for the DAC output to settle to within
±1/2 LSB (0.0125%) of its final value.
The DAC312 switching transients or “glitches” are on the order
of 500 mV-ns. This is most evident when switching through the
major carry and may be further reduced by adding small capaci-
tive loads at the output with a minor sacrifice in transition speeds.
Fastest operation can be obtained by using short leads, minimiz-
ing output capacitance and load resistor values, and by adequate
bypassing at the supply, reference, and VLC terminals. Supplies
do not require large electrolytic bypass capacitors as the supply
current drain is independent of input logic states; 0.1
F capaci-
tors at the supply pins provide full transient protection.
相關PDF資料 |
PDF描述 |
|---|---|
| D38999/20SD19PN | CONN RCPT 19POS WALL MNT W/PINS |
| VI-BNX-MV-F1 | CONVERTER MOD DC/DC 5.2V 150W |
| MS27484E16B6SA | CONN PLUG 6POS STRAIGHT W/SCKT |
| VI-J5L-MZ-F4 | CONVERTER MOD DC/DC 28V 25W |
| AD7533KRZ | IC DAC 10BIT MULTIPLYING 16-SOIC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DAC312HR | 制造商:PMI 功能描述: |
| DAC312HS | 功能描述:IC DAC 12BIT MULTIPLY HS 20-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:47 系列:- 設置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| DAC312HS-REEL | 功能描述:IC DAC 12BIT MULT HS 20-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:2,400 系列:- 設置時間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應商設備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| DAC312HSZ | 功能描述:IC DAC 12BIT MULTIPLY HS 20-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| DAC312HSZ-REEL | 功能描述:IC DAC 12BIT MULT HS 20SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產(chǎn)品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標準包裝:91 系列:- 設置時間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤 供應商設備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
發(fā)布緊急采購，3分鐘左右您將得到回復。