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參數(shù)資料
| 型號(hào)： | DAC1331X |
| 英文描述： | DAC1331X 10BIT 40MSPS DAC|Data Sheet |
| 中文描述： | DAC1331X 10位40MSPS援會(huì)|數(shù)據(jù)資料 |
| 文件頁數(shù)： | 15/15頁 |
| 文件大?。?/td> | 228K |
| 代理商： | DAC1331X |
SEC ASIC
DAC1350X
10BIT 75MSPS Quad DAC
ANALOG
TIMING DIAGRAM
NOTES
1. The Behavioral Modeling is provided by Verilog
2. Output delay(Td) measured from the 50% point of the rising edge of CLK to the full scale trasition
3. Settling time(Tset) measured from the 50% point of full scale transition to the output remaining
within ±1LSB iteration.
4. Output rising(Tr)/falling(Tf) time measured between the 10% and 90% points of full scale transition.
5. Any power_down doesn't need clock signal.
6. PDDAC#
makes the channel down respectively when it is high.
7. PDDAC#
have absolutely no relations among them.
8. BGPD makes all of the blocks disable regardless of PDDAC#.
9. The minimum Pulse Width Low of BGPD should be longer than 500us.
10. The minimum Pulse Width Low of PDDAC# should be longer than 50us.
11. The minimum Pulse Width Low of BGPD and PDDAC# should be longer than 20ns.
9 / 15
Analog
Output
CLK
Digital
Input
D (1)
t
d
DI (2)
DI (3)
DI (4)
1/2 CLK PIPELINE DELAY
DI (5)
AO (1)
AO (2)
AO (3)
TselL TSPWL
Tdet_val
DLDSEL[1:0]
PRE
DETECT
DAC0
DAC0's load detect
DATA#[9:0]
IOUT(voltage measure)
PDDAC#
data#(1111111111)
Tpn
Tpf
0V
Vout(pp)
Analog output Delay
Load detection timing
Power Down timing
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