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參數(shù)資料
| 型號： | DAC1221E |
| 英文描述： | 16-Bit Low Power DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 16位低功耗數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 125K |
| 代理商： | DAC1221E |
11
DAC1221
t
1
t
3
t
4
t
2
t
2
SCLK
Reset On
Falling Edge
FIGURE 3. Resetting the DAC1221.
t
1
: > 512 t
XIN
< 800 t
XIN
t
2
: > 10 t
XIN
t
3
: > 1024 t
XIN
< 1800 t
XIN
t
4
:
≥
2048 t
XIN
< 2400 t
XIN
I/O Recovery
If serial communication stops during an instruction or data
transfer for longer than 100ms (for f
XIN
= 2.5MHz), the
DAC1221 will reset its serial interface. This will not affect
the internal registers. The main controller must not continue
the transfer after this event, but must restart the transfer from
the beginning. This feature is very useful if the main control-
ler can be reset at any point. After reset, simply wait 200ms
(for f
XIN
= 2.5MHz) before starting serial communication.
Isolation
The serial interface of the DAC1221 provides for simple
isolation methods. An example of an isolated two-wire
interface is shown in Figure 4.
Using CS
The serial interface may make use of the CS signal, or this
input may simply be tied LOW. There are several issues
associated with choosing to do one or the other. The CS
signal does not directly control the tri-state condition of the
SDIO output. These signals are normally in the tri-state
condition. They only become active when serial data is
being transmitted from the DAC1221. If the DAC1221 is in
the middle of a serial transfer and the SDIO is an output,
taking CS HIGH will not tri-state the output signal.
If there are multiple serial peripherals utilizing the same
serial I/O lines and communication may occur with any
peripheral at any time, the CS signal must be used. The CS
signal is then used to enable communication with the
DAC1221.
TIMING
The maximum serial clock frequency cannot exceed the
DAC1221 X
IN
frequency divided by 10. Table VIII and
Figures 5 through 9 define the basic digital timing character-
istics of the DAC1221. Figure 5 and the associated timing
symbols apply to the X
IN
input signal. Figures 6 through 9
and associated timing symbols apply to the serial interface
signals (SCLK, SDIO, and CS). The serial interface is
discussed in detail in the Serial Interface section.
1
2
3
4
5
6
7
8
DV
DD
X
OUT
X
IN
DGND
AV
DD
DNC
C
3
C
2B
SCLK
SDIO
CS
AGND
V
REF
V
OUT
C
2A
C
1
16
15
14
13
12
11
10
9
DAC1221
C
5.6pF
C
5.6pF
AV
DD
XTAL
V
REF
DV
DD
P1.1
P1.0
8051
Opto
Coupler
Opto
Coupler
Isolated
Power
C
2
C
3
C
1
= DGND
= AGND
= Isolated
FIGURE 4. Isolation for Two-Wire Interface.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC1221E/2K5 | 制造商:Rochester Electronics LLC 功能描述:D/A CONV, 16-BIT 3V - Bulk |
| DAC1221EG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 16B Delta-Sigma Low Power DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC1221LCN | 制造商:n/a 功能描述:1221 |
| DAC1221LCN/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12-Bit Digital-to-Analog Converter |
| DAC1221LCN/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12-Bit Digital-to-Analog Converter |
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