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參數(shù)資料
| 型號： | DAC1205D650HW |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 12-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating |
| 封裝： | DAC1205D650HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT638-1.html<1<Always Pb-free,;DAC1205D650HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT6 |
| 文件頁數(shù)： | 28/43頁 |
| 文件大?。?/td> | 295K |
| 代理商： | DAC1205D650HW |
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DAC1205D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 13 September 2010
28 of 43
NXP Semiconductors
DAC1205D650
Dual 12-bit DAC, up to 650 Msps; 2
×
4
×
and 8
×
interpolating
The reference current is generated using an external resistor of 910
Ω
(1 %) connected to
pin VIRES. A control amplifier sets the appropriate full-scale current (I
O(fs)
) for both DACs
(see
Figure 11 “Internal reference configuration”
).
This configuration is optimum for temperature drift compensation because the bandgap
reference voltage can be matched to the voltage across the feedback resistor.
The DAC current can also be set by applying an external reference voltage to the
non-inverting input pin GAPOUT and disabling the internal bandgap reference voltage
with GAP_PD (register 00h[0]; see
Table 10 “COMMon register (address 00h) bit
description”
).
10.10.2
Full-scale current adjustment
The default full-scale current (I
O(fs)
) is 20 mA. It can be further adjusted for each DAC
using SPI. The adjustment range is between 1.6 mA and 22 mA,
±
10 %.
The settings applied to DAC_A_GAIN_COARSE[3:0] (register 0Ah; see
Table 20
“DAC_A_Cfg_2 register (address 0Ah) bit description”
and register 0Bh; see
Table 21
“DAC_A_Cfg_3 register (address 0Bh) bit description”
) and to DAC_B_GAIN
COARSE[3:0] (register 0Dh; see
Table 23 “DAC_B_Cfg_2 register (address 0Dh) bit
description”
and register 0Eh; see
Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit
description”
) define the coarse variation of the full-scale current (see
Table 36 “I
O(fs)
coarse adjustment”
).
Table 36.
Default settings are shown highlighted.
DAC_GAIN_COARSE[3:0]
Decimal
0
1
2
3
4
5
6
7
Fig 11. Internal reference configuration
001aaj816
REF.
BANDGAP
GAPOUT
VIRES
DAC
CURRENT
SOURCES
ARRAY
AGND
AGND
100 nF
909
Ω
(1 %)
I
O(fs)
coarse adjustment
I
O(fs)
(mA)
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1.6
3.0
4.4
5.8
7.2
8.6
10.0
11.4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC1205D650HW/C1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 12-bit DAC, up to 650 Msps; 2′ 4′ and 8′ interpolating |
| DAC1205D650HW/C1,5 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC DAC 12BIT 650MSPS DL RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC1205D650HW-C1 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC DAC RoHS:否 制造商:IDT 轉(zhuǎn)換器數(shù)量:2 DAC 輸出端數(shù)量:4 轉(zhuǎn)換速率:650 MSPs 分辨率:12 bit 接口類型:Serial, SPI 穩(wěn)定時(shí)間:20 ns 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-100 封裝: |
| DAC1205D650HW-C18 | 制造商:Integrated Device Technology Inc 功能描述:BST - Tape and Reel |
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