參數(shù)資料
型號: DAC1005D750HW
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 10-bit DAC, up to 750 Msps; 2x 4x and 8x interpolating
中文描述: PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 10-BIT DAC, PQFP100
封裝: 14 X 14 MM, 1 MM HEIGHT, PLASTIC, MS-026, SOT638-1, HTQFP-100
文件頁數(shù): 14/42頁
文件大?。?/td> 353K
代理商: DAC1005D750HW
DAC1005D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 June 2011
14 of 42
NXP Semiconductors
DAC1005D750
Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating
Table 6.
R/W
0
1
In
Table 7
N1 and N0 indicate the number of bytes transferred after the instruction byte.
Table 7.
N1
0
0
1
1
A0 to A4: indicate which register is being addressed. In the case of a multiple transfer, this
address concerns the first register after which the next registers follow directly in a
decreasing order according to
Table 9 “Register allocation map”
.
10.2.2
SPI timing description
The interface can operate at a frequency of up to 15 MHz. The SPI timing is shown in
Figure 4
.
R/W indicates the mode access, (see
Table 6
).
Fig 3.
SPI protocol
001aaj812
RESET_N
SCS_N
SCLK
SDIO
SDO
(optional)
R/W
N1
N0
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Read or Write mode access description
Description
Write mode operation
Read mode operation
Number of bytes transferred
N0
0
1
0
1
Number of bytes
1 byte transferred
2 bytes transferred
3 bytes transferred
4 bytes transferred
Fig 4.
SPI timing diagram
001aaj813
50 %
t
w(RESET_N)
t
su(SCS_N)
t
su(SDIO)
t
h(SDIO)
t
h(SCS_N)
t
w(SCLK)
50 %
RESET_N
SCS_N
SCLK
SDIO
50 %
50 %
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