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參數(shù)資料
| 型號(hào)： | CZ80PIO |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Hereinafter Referred to As PIO, is a Dual-Port Device |
| 中文描述： | 以下簡稱為先鋒，是一個(gè)雙端口器件 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 165K |
| 代理商： | CZ80PIO |
CZ80PIO Megafunction Datasheet
CAST, Inc.
Page 2
Pin Description
Name
Type Description
Clock
clk
Interface to Processor
data_tri
Out Tristate controller for buffer for data
bus
data_i
In
Data bus input
data_o
Out Data bus output:
rd_n
In
Read Cycle Status
iorq_n
In
Input / Output Request
ce_n
In
Chip Enable
cdselect
In
Control / Data select
portselect In
Port B / A select
m1_n
In
Machine Cycle One
Interrupt Service Routine
int_n
In
Interrupt Request
iei
In
Interrupt Enable Input
ieo
Out Interrupt Enable Output
Control
porta_tri
In
Tristate controller for buffer for data
bus
porta_i
In
Port B bus input
porta_o
Out Port B bus output
portb_tri
In
Tristate controller for buffer for data
bus
portb_i
In
Port B bus input
portb_o
Out Port B bus output
ardy
Out Register A ready
brdy
Out Register B ready
astb_n
In
Port A strobe pulse from peripheral
device
bstb_n
In
Port B strobe pulse from peripheral
device
In
System Clock
Functional Description
The CZ80PIO megafunction is partitioned into
modules as shown in figure 1 and described
below.
Port Logic
Each port contains separate input and output
registers, handshake control logic and the
control registers. All data transfers between the
peripheral unit and the CPU use the data input
and output registers. The handshake logic
associated with each port controls the data
transfers through the input and the output
registers. The mode control register (two bits)
selects one of the four programmable operating
modes. The Bit Control mode (mode 3) uses the
remaining registers. The input/output control
register specifies which of the eight data bits in
the port are to be outputs and enables these
bits; the remaining bits are inputs. The mask
register specifies which of the bits in the port
are masked
.
Control logic
The control logic consists of the CPU bus
interface logic, interrupt control logic and internal
control logic. The CPU bus interface logic
interfaces the CZ80PIO directly to the CZ80CPU,
so no external logic is necessary. For large
systems, however, address decoders and/or
buffers may be necessary. The interrupt control
logic section handles all CPU interrupt protocol
for nested-priority interrupt structures. Any
device's physical location in a daisy-chain
configuration determines its priority. Two lines
(IEO and IEI) are provided in each PIO to form
this daisy chain. The device closest to the CPU
has the highest priority. Within a PIO, port A
interrupts have higher priority then those of port
B. In the byte input, byte output or bi-directional
modes, an interrupt can be generated whenever
the peripheral requests a new byte transfer. In
the bit control mode, an interrupt can be
generated when the peripheral status matches a
programmed value.
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