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PRELIMINARY
CYWUSB6953
Document #: 38-16017 Rev. *C
Page 2 of 7
Functional Overview
The CYWUSB6953 is a complete Radio System-on-Chip
device, enabling many simple RF systems to be implemented
with a single device and a handful of discrete components. The
CYWUSB6953 is designed to implement low cost wireless
systems operating in the worldwide 2.4-GHz Industrial, Scien-
tific, and Medical (ISM) frequency band (2.400 GHz–2.4835
GHz).
The radio meets the following world-wide regulatory require-
ments:
Europe
ETSI EN 301 489-1 V1.4.1
ETSI EN 300 328-1 V1.3.1
North America
FCC CFR 47 Part 15
Japan
ARIB STD-T66
The microcontroller is a powerful mixed-signal array. It has
highly reconfigurable and flexible digital and analog blocks.
The microcontroller core is the M8C 8-bit engine that supports
a rich instruction set. It contains 512 Bytes of data SRAM and
8 Kbytes code Flash memory. Full data on the microcontroller
can be found in the CY8C21534 datasheet and the PSoC
Technical Reference Manual
The radio is a high-performance 2.4-GHz transceiver with a
fully integrated DSSS baseband. The radio and baseband are
both code and frequency agile. Protocols supporting
frequency
agile
direct-spread
algorithms such as WirelessUSB are fully compatible with this
radio. Full data on the radio can be found in the CYWUSB6935
data sheet.
interference
avoidance
Radio Data Rate Considerations
The PSoC Designer tool provides a software-based SPI User
Module for control of the radio portion of the PRoC. Therefore,
there is a direct relationship between CPU clock speed and
supportable radio data rate. For operation of CPU clock rates
less than 12 MHz, radio data rate must be set to 16 Kbps. Also
note that for operation at V
CC
< 3.0V, the CPU clock rate must
be set to 3 MHz per the CY8C21534 data sheet. Therefore, at
operation below 3V, the radio data rate must be set to 16 Kbps.
Digital PSoC
Block Array
Analog PSoC
Block Array
System Resources
Clocks, I2C, POR, Ref
PSoC M8C Core
8KB Flash
512B
SRAM
IO Ports
2.4-GHz WirelessUSB
Radio Transceiver
RFIN
RFOUT
XRES
X13_OUT
PACTL
P0 P1 P2
IRQ, MISO
PRoC Block Diagram
Figure 2. PROC Block Diagram