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參數(shù)資料
| 型號(hào)： | CYW3335 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 諧振器 |
| 英文描述： | Dual Serial Input PLL with 2.5-GHz Prescalers(帶2.5-GHz 預(yù)標(biāo)定器的串聯(lián)輸入PLL) |
| 中文描述： | DUAL PRESCALER, PDSO20 |
| 封裝： | 0.173 INCH, MO-153, TSSOP-20 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 158K |
| 代理商： | CYW3335 |
CYW3335
3
Pin Definitions
Pin Name
Pin
No.
Pin
Type
Pin Description
V
CC
1
P
Power Supply Connection for PLL1 and PLL2:
When power is removed from both
the V
CC
1 and V
CC
2 pins, all latched data is lost.
PLL1 Charge Pump Rail Voltage:
This voltage accommodates VCO circuits with
tuning voltages higher than the V
CC
of PLL1.
PLL1 Charge Pump Output:
The phase detector gain is I
P
/2
π
. Sense polarity can be
reversed by setting the FC bit in software (via the Shift Register).
Analog and Digital Ground Connection:
This pin must be grounded.
V
P
1
2
P
D
O
PLL1
3
O
GND
4
G
F
IN
1
F
IN
1#
5
I
Input to PLL1 Prescaler:
Maximum frequency 2.5 GHz.
Complementary Input to PLL1 Prescaler:
A bypass capacitor should be placed as
close as possible to this pin and must be connected directly to the ground plane.
Analog and Digital Ground Connection:
This pin must be grounded.
6
I
GND
7
G
OSC_IN
8
I
Oscillator Input:
This input has a V
CC
/2 threshold and CMOS logic level sensitivity.
Reference Ground Connection:
This pin must be grounded.
GND
9
G
F
O
/LD
10
O
Lock Detect Pin of PLL1 Section:
This output is HIGH when the loop is locked. It is
multiplexed to the output of the programmable counters or reference dividers in the
test program mode. (Refer to
Table 3
for configuration.)
CLOCK
11
I
Data Clock Input:
One bit of data is loaded into the Shift Register on the rising edge
of this signal.
DATA
12
I
Serial Data Input
Load Enable:
On the rising edge of this signal, the data stored in the Shift Register
is latched into the reference counter and configuration controls, PLL1 or PLL2 depend-
ing on the state of the control bits.
Analog and Digital Ground Connection:
This pin must be grounded.
LE
13
I
GND
14
G
F
IN
2#
15
I
Complementary Input to PLL2 Prescaler:
A bypass capacitor should be placed as
close as possible to this pin and must be connected directly to the ground plane.
Input to PLL2 Prescaler:
Maximum frequency 2.5 GHz.
F
IN
2
GND
16
I
17
G
Analog and Digital Ground Connections:
This pin must be grounded.
PLL2 Charge Pump Output:
The phase detector gain is I
P
/2
π
. Sense polarity can be
reversed by setting the FC bit in software (via the Shift Register).
PLL2 Charge Pump Rail Voltage:
This voltage accommodates VCO circuits with
tuning voltages higher than the V
CC
of PLL2.
Power Supply Connections for PLL1 and PLL2:
When power is removed from both
the V
CC
1 and V
CC
2 pins, all latched data is lost.
D
O
PLL2
18
O
V
P
2
19
P
V
CC
2
20
P
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