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| 型號： | CYW15G0403DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| 中文描述： | 獨立時鐘四路HOTLink II收發(fā)器（獨立時鐘，四熱連接二收發(fā)器） |
| 文件頁數(shù)： | 10/43頁 |
| 文件大小： | 744K |
| 代理商： | CYW15G0403DXB |
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CYV15G0403DXB
CYW15G0403DXB
CYP15G0403DXB
Document #: 38-02065 Rev. *E
Page 10 of 43
ADDR[3:0]
LVTTL input
asynchronous,
internal pull-up
Control Addressing Bus
. The ADDR[3:0] bus is the input address bus used to
configure the device. The WREN input writes the values of the DATA[7:0] bus into the
latch specified by the address location on the ADDR[3:0] bus.
[5]
Table 9
lists the
configuration latches within the device, and the initialization value of the latches upon
the assertion of RESET.
Table 10
shows how the latches are mapped in the device.
DATA[7:0]
LVTTL input
asynchronous,
internal pull-up
Control Data Bus
. The DATA[7:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[7:0] bus into the latch
specified by address location on the ADDR[3:0] bus.
[5 ]
Table 9
lists the configuration
latches within the device, and the initialization value of the latches upon the assertion
of RESET.
Table 10
shows how the latches are mapped in the device.
Internal Device Configuration Latches
RFMODE[A..D][1:0] Internal Latch
[6]
FRAMCHAR[A..D] Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
SDASEL[A..D][1:0] Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Reframe Mode Select
.
Framing Character Select
.
DECMODE[A..D]
Receiver Decoder Mode Select
.
DECBYP[A..D]
Receiver Decoder Bypass
.
RXCKSEL[A..D]
Receive Clock Select
.
RXRATE[A..D]
Receive Clock Rate Select
.
Signal Detect Amplitude Select
.
ENCBYP[A..D]
Transmit Encoder Bypassed
.
TXCKSEL[A..D]
Transmit Clock Select
.
TXRATE[A..D]
Transmit PLL Clock Rate Select
.
RFEN[A..D]
Reframe Enable
.
RXPLLPD[A..D]
Receive Channel Power Control
.
RXBIST[A..D]
Receive Bist Disabled
.
TXBIST[A..D]
Transmit Bist Disabled
.
OE2[A..D]
Differential Serial Output Driver 2 Enable
.
OE1[A..D]
Differential Serial Output Driver 1 Enable
.
PABRST[A..D]
Transmit Clock Phase Alignment Buffer Reset
.
GLEN[11..0]
Global Latch Enable
.
FGLEN[2..0]
Force Global Latch Enable
.
Factory Test Modes
LTEN1
LVTTL input,
internal pull-down
Factory Test 1
. LTEN1 input is for factory testing only. This input may be left as a NO
CONNECT, or GND only.
SCANEN2
LVTTL input,
internal pull-down
Factory Test 2.
SCANEN2 input is for factory testing only. This input may be left as
a NO CONNECT, or GND only.
TMEN3
LVTTL input,
internal pull-down
Factory Test 3
. TMEN3 input is for factory testing only. This input may be left as a
NO CONNECT, or GND only.
Note:
6.
See
Device Configuration and Control Interface
for detailed information on the internal latches.
Pin Descriptions
(continued)
CYP(V)(W)15G0403DXB Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
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| CYW15G0403DXB-BGC | 功能描述:電信線路管理 IC Quad Indep CH XCVR COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYW15G0403DXB-BGI | 功能描述:電信線路管理 IC Quad Indep CH XCVR IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYW15G0403DXB-BGXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver |
| CYW15G0403DXB-BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver |
| CYW15GO403DXB-BGI | 制造商:Cypress Semiconductor 功能描述: |
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