參數(shù)資料
型號(hào)： CYP15G04K100V1
英文描述： Physical Layer Devices
中文描述： 物理層設(shè)備
文件頁(yè)數(shù)： 1/78頁(yè)
文件大小： 1555K
代理商： CYP15G04K100V1
PRELIMINARY
Programmable Serial Interface (Frequency Agile Devices)
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
Cypress Semiconductor Corporation
Document #: 38-02044 Rev. **
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised January 29, 2002
Features
200 Mbps–1.5 Gbps, 2.5 Gbps serial signaling rate
Flexible parallel-to-serial conversion in transmit path
Flexible serial-to-parallel conversion in receive path
Multiple selectable loopback/loop-through modes
100k to 200k usable gates of CPLD logic
240k to 480k bits of integrated memory
—192k to 384k bits of synchronous or asynchronous
SRAM
—48k to 96k bits of true Dual-Port or FIFO RAM
Internal transmit and receive PLLs
Logic dedicated Spread Aware PLL
Transmit FIFO for flexible variable phase clocking
Differential CML serial input with internal termination
and DC-restoration
Differential CML serial output with source matched im-
pedance of 50
160–240 user programmable I/Os
AnyVolt I/O interface
—Programmable as 1.8V, 2.5V, 3.3V
Multiple I/O standards
—LVCMOS, LVTTL, 3.3V PCI, SSTL2(I-II), SSTL3(I-II),
HSTL(I-IV), and GTL+
Direct interface to standard fiber-optic modules
Designed to drive:
—fiberoptic modules
—copper cables
—circuit board traces
—backplane links
—box-to-box links
—chip-to-chip communication
Supported standards:
—Fibre Channel
—Gigabit Ethernet
—ESCON
—DVB
—SMPTE 259 and 292
Extremely flexible clocking options
—Four global clocks
—Up to 192 additional product term clocks
—Clock polarity at every register
Carry chain logic for fast and efficient arithmetic oper-
ations
PCI compliant (Rev. 2.2)
JTAG programming interface with boundary scan sup-
port
High-Speed (HS) or Frequency Agile (FA) Programma-
ble Serial Interface (PSI) versions available
Frequency Agile PSI Features
200 Mbps–1.5 Gbps serial signaling rate per channel
Up to eight serial channels available to allow:
—Frequency Agile
—Redundancy
Selectable input and output clocking options
MultiFrame receive framer provides alignment to:
—Bit, byte, half-word, word, multi-word
—COMMA or Full K28.5 detect
—Single or Multi-byte framer for byte alignment
—Low-latency option
Skew alignment support for multiple bytes of offset
Serial Built-In-Self-Test (BIST) for at-speed link testing
Per-channel Link Quality Indicator
—Analog signal detect
—Digital signal detect
—Frequency range detect
High-Speed PSI Features
[1]
2.5 Gbps/channel serial signaling rate
Full Bellcore and ITU jitter compliance
Power-saving mode
Up to two serial channels available to allow:
—High-Bandwidth
—Redundancy
Supported standards:
—InfiniBand
—SONET/SDH OC-48
Development Software
Warp
—
IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing
—
Active-HDL FSM graphical finite state machine
editor
—
Active-HDL SIM post-synthesis timing simulator
—
Architecture Explorer for detailed design analysis
—
Static Timing Analyzer for critical path analysis
—
Available on Windows 95, 98 & NT for $99
—
Supports all Cypress programmable logic products
Note:
1.
For detailed data sheet see
“
High-Speed PSI data sheet.
”
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