參數(shù)資料
型號(hào)： CYNSE70032-83BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Network Search Engine
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA272
封裝： 27 X 27 MM, 2.33 MM HEIGHT, BGA-272
文件頁數(shù)： 115/126頁
文件大?。?/td> 3333K
代理商： CYNSE70032-83BGC
CYNSE70032
Document #: 38-02042 Rev. *E
Page 115 of 126
18.0
JTAG (1149.1) Testing
The CYNSE70032 supports the Test Access Port (TAP) and Boundary Scan Architecture, as specified in the IEEE JTAG standard
1149.1. The pin interface to the chip consists of five signals with the standard definitions: TCK, TMS, TDI, TDO, and TRST_L.
Table 18-1
describes the operations that the test access port controller supports, and
Table 18-2
describes the TAP Device ID
Register.
Note
. To disable JTAG functionality, connect the TCK, TMS and TDI pins to V
DDQ
through a pull-up, and TRST_L to
ground through a pull-down.
Table 18-1. Supported Operations
Instruction
SAMPLE/PRELOAD
Type
Description
Mandatory
Sample/Preload
. This operation loads the values of signals going to and from I/O
pins into the boundary scan shift register to provide a snapshot of the normal
functional operation, and to initialize the boundary scan.
External Test
. This operation uses boundary scan values shifted in from TAP to
test connectivity external to the device.
This operation loads a single bit shift register between TDI and TDO
and
provides a minimum-length serial path when no test operation is required.
This operation selects the Identification register between TDI and TDO
and
allows the “idcode” to be read serially through TDO.
This operation drives preset values onto the outputs of devices
.
This operation leaves the device output pins in a high impedance state
.
EXTEST
Mandatory
BYPASS
Mandatory
IDCODE
Optional
CLAMP
HIghZ
Optional
Optional
Pogam
Memoy
Network Line Interfaces
System Bus
Pocesso
Swtch
Fabic
ASC
Seach
Engne
SRBank
Figure 17-1. Sample Switch/Router Using the CYNSE70032 Device
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