參數(shù)資料
型號(hào)： CYNCP80192
英文描述： Network Processing
中文描述： 網(wǎng)絡(luò)處理
文件頁(yè)數(shù)： 30/42頁(yè)
文件大小： 679K
代理商： CYNCP80192
CYNCP80192
Document #: 38-02043 Rev. *B
Page 30 of 42
15.0
JTAG (1149.1) Testing
The CYNPC80192 supports the Test Access Port and Boundary Scan Architecture as specified in the IEEE JTAG Standard
1149.1. The pin interface to the chip consists of five signals with the standard definitions: TCK, TMS, TDI, TDO, and TRST_L.
Table 15-1
and
Table 15-2
describe the operations that the test access port controller supports and the test access port device
ID register.
Table 15-1. Test Access Port Controller Instructions
Instruction
SAMPLE/PRELOAD Mandatory
Sample/Preload
. Loads the values of signals going to and from I/O pins into the boundary
scan shift register to provide a snapshot of the normal functional operation.
EXTEST
Mandatory
External Test
. Uses boundary scan values shifted in from TAP to test connectivity external to
the device.
INTEST
Optional
Internal Test
. Allows slow-speed functional testing of the device using the boundary scan
register to provide the I/O values.
Type
Description
Table 15-2. Test Access Port Device ID Register
Field
Revision
Range
[31:28]
Initial Value
0001
Description
Revision Number
. This is the current device revision number. Numbers start
from one and increment by one for each revision of the device.
0000 0000 0000 0011
This is the part number for this device
.
000_1101_1100
Manufacturer ID
. This field is the same as the manufacturer ID used in the TAP
controller.
1
Least Significant Bit
.
Part Number
MFID
[27:12]
[11:1]
LSB
0
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