參數(shù)資料
型號(hào): CYM9262A
廠商: Cypress Semiconductor Corp.
英文描述: 256K x 72 SRAM Module(256K x 72 靜態(tài)RAM模塊)
中文描述: 256 × 72的SRAM模塊(256 × 72靜態(tài)內(nèi)存模塊)
文件頁數(shù): 7/11頁
文件大小: 246K
代理商: CYM9262A
CYM9260
CYM9261B
CYM9262A
CYM9263
7
AC Test Loads and Waveforms
[3]
3.3V
GND
90%
10%
90%
10%
3 ns
3 ns
OUTPUT
R1
R2
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
ALL INPUT PULSES
9260-5
9660-6
OUTPUT
R
L
= 50
V
L
=1.5V
V
CCQ
[2]
Switching Characteristics
Over the Operating Range
Parameter
Description
CYM9260/61/62/63
66 MHz
50 MHz
Min
Max
Min
Max
Unit
t
CYC
t
CH
t
CL
t
AS
t
AH
t
CDV
t
DOH
t
ADS
t
ADSH
t
WES
t
WEH
t
DS
t
DH
t
CSS
t
CSH
t
EOZ
t
EOV
Notes:
2.
3.
Clock Cycle Time
15
20
ns
Clock HIGH
6
8
ns
Clock LOW
6
8
ns
Address Set-Up Before CLK Rise
3.1
3.1
ns
Address Hold After CLK Rise
0.5
0.5
ns
Data Output Valid After CLK Rise
10.3
14
ns
Data Output Hold After CLK Rise
3
3
ns
ADSP ADSC Set-Up Before CLK Rise
3.1
3.1
ns
ADSP ADSC Hold After CLK Rise
0. 5
0.5
ns
WH, WL Set-Up Before CLK Rise
3.1
3.1
ns
WH, WL Hold After CLK Rise
0.5
0.5
ns
Data Input Set-Up Before CLK Rise
3.3
3.3
ns
Data Input Hold After CLK Rise
0.5
0.5
ns
Chip Select Set-Up
3.1
3.1
ns
Chip Select Hold After CLK Rise
OE HIGH to Output High Z
[4]
0.5
0.5
ns
7
7
ns
OE LOW to Output Valid
7
7
ns
Resistor values for V
=3.3V are R1= 317
and R2= 351
.
Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified I
/I
and load capacitance. Shown in (a) and (b) of AC test loads. All measurements are made at room temperature.
t
EOZ
is specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
4.
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