參數(shù)資料
型號: CYM9260-50C
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: GIGATRUE CAT6 UNIVERSAL JACK, YELLOW
中文描述: 64K X 72 CACHE SRAM MODULE, 14 ns, DMA168
封裝: DIMM-168
文件頁數(shù): 7/12頁
文件大?。?/td> 207K
代理商: CYM9260-50C
CYM9260
CYM9261B
CYM9262A
CYM9263
Document #: 38-05002 Rev. **
Page 7 of 12
AC Test Loads and Waveforms
[3]
3.3V
GND
90%
10%
90%
10%
3 ns
3 ns
OUTPUT
R1
R2
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
ALL INPUT PULSES
OUTPUT
R
L
= 50
V
L
=1.5V
V
CCQ
[2]
Switching Characteristics
Over the Operating Range
Parameter
t
CYC
t
CH
t
CL
t
AS
t
AH
t
CDV
t
DOH
t
ADS
t
ADSH
t
WES
t
WEH
t
DS
t
DH
t
CSS
t
CSH
t
EOZ
t
EOV
Notes:
2.
Resistor values for V
= 3.3V are R1 = 317
and R2 = 351
.
3.
Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified I
/I
and load capacitance. Shown in (a) and (b) of AC Test Loads. All measurements are made at room temperature.
4.
t
EOZ
is specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
Description
CYM9260/61/62/63
66 MHz
Min.
Max.
15
6
6
3.1
0.5
10.3
3
3.1
0. 5
3.1
0.5
3.3
0.5
3.1
0.5
7
7
50 MHz
Min.
20
8
8
3.1
0.5
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Time
Clock HIGH
Clock LOW
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
WH, WL Set-Up Before CLK Rise
WH, WL Hold After CLK Rise
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip Select Set-Up
Chip Select Hold After CLK Rise
OE HIGH to Output High Z
[4]
OE LOW to Output Valid
14
3
3.1
0.5
3.1
0.5
3.3
0.5
3.1
0.5
7
7
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