參數(shù)資料
型號(hào)： CYM74SP55
廠商： Cypress Semiconductor Corp.
英文描述： 82430NX Chipset Level II Cache Module Family(82430NX 芯片組電平II 高速緩沖存儲(chǔ)器模塊系列)
中文描述： 82430NX芯片組二級(jí)緩存模塊系列（82430NX芯片組電平二高速緩沖存儲(chǔ)器模塊系列）
文件頁(yè)數(shù)： 5/7頁(yè)
文件大小： 198K
代理商： CYM74SP55
CYM74BP54
CYM74P54/55
CYM74SP54/55
PRELIMINARY
5
Pin Definitions
Common Signals
Description
V
CC
GND
A
7
–A
19
A
3–0
, A
4–0
A
3–1
, A
4–1
5V Supply
Ground
Addresses from processor
Lower address from chipset, identical to the bank1 addresses
Lower address from chipset, identical to the bank0 addresses, A
3-1
, A
4-1
not used on
CYM74P54
Lower address from processor (CYM74P5X, CYM74SP5X- identical to the bank1
addresses)
Chip Enable (same signal), CE
1
not used on CYM74P54
Output Enable (same signal), OE
1
not used on CYM74P54
Byte Write Enables
A
5–0
, A
6–0
CE
0
, CE
1
OE
0
, OE
1
WE
0
, WE
1
,WE
2
,WE
3
WE
4
,WE
5
,WE
6
,WE
7
PD
0
–PD
2
D
0
–D
63
NC
CYM74BP54 Only Signals
CALE
CYM74P5X, CYM74SP5X Signals
V
CCQ
DP
0
–DP
7
ADSP0, ADSP1
ADSC0,ADSC1
ADV0, ADV1
A
5–1
, A
6–1
Presence Detect pins
Data lines from processor
Signal not connected on module.
Description
Latch Enable
Description
3.3V Supply
Data Parity lines (Optional)
Processor Address Strobe, ADSP1 not used on CYM74P54
Cache Controller Address Strobe, ADSC1 not used on CYM74P54
Burst Address Advance, ADV1 not used on CYM74P54
Lower address from processor, identical to the bank0 addresses, A
5-1
, A
6-1
not used on
CYM74P54
Clock signals (each should be given own clk driver); CLK0 used on CYM74P5X,
CYM74SP5X; CLK1 not used on CYM74P54; CLK2 and CLK3 are RSVD
CLK0, CLK1, CLK2, CLK3
Presence Detect Pins
PD
2
NC
TBD
TBD
GND
GND
PD
1
GND
TBD
TBD
GND
GND
PD
0
NC
TBD
TBD
NC
GND
Asynchronous – CYM74BP54
Synchronous Pipelined – CYM74P54
Synchronous Pipelined – CYM74P55
Synchronous Burst – CYM74SP54
Synchronous Burst – CYM74SP55
相關(guān)PDF資料
PDF描述
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