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參數(shù)資料
| 型號(hào)： | CYM1851PZ-35C |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 1,024K x 32 Static RAM Module |
| 中文描述： | 1M X 32 MULTI DEVICE SRAM MODULE, 35 ns, PZMA72 |
| 封裝： | PLASTIC, ZIP-72 |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大?。?/td> | 357K |
| 代理商： | CYM1851PZ-35C |
CYM1851
Document #: 38-05274 Rev. **
Page 3 of 9
AC Test Loads and Waveforms
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
< 5 ns
< 5 ns
OUTPUT
R1 481
R1 481
R2
255
R2
255
167
Equivalent to:
TH
é
VENIN
EQUIVALENT
1.73V
Switching Characteristics
Over the Operating Range
[3]
1851-12
Min.
1851-15
Min.
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
t
PD
WRITE CYCLE
[6]
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes:
3.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
4.
At any given temperature and voltage condition, t
is less than t
for any given device. These parameters are guaranteed and not 100% tested.
5.
t
and t
are specified with C
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±
500 mV from steady-state voltage.
6.
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Description
Max.
Max.
Unit
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CS LOW to Low Z
[4]
CS HIGH to High Z
[4, 5]
CS HIGH to Power-Down
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
15
3
3
12
7
15
8
0
0
7
8
3
3
7
8
12
15
Write Cycle Time
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
[5]
12
9
9
0
1
10
7
1
3
0
15
10
10
0
1
12
8
1
3
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
8
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