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參數(shù)資料
| 型號(hào)： | CYM1846V33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512K x 32 3.3V Static RAM Module(512K x 32 3.3V 靜態(tài)RAM模塊) |
| 中文描述： | 512k × 32的3.3V的靜態(tài)存儲(chǔ)器模塊（512k × 32的3.3V的靜態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 115K |
| 代理商： | CYM1846V33 |
CYM1846V33
PRELIMINARY
3
AC Test Loads and Waveforms
1846v33
–
4
1846v33
–
5
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
≤
5 ns
≤
5ns
OUTPUT
R1 315
R1 315
R2
351
R2
351
167
Equivalent to:
TH
é
VENIN
EQUIVALENT
1.73V
(c)
1846v33
–
3
Switching Characteristics
Over the Operating Range
[4]
1846V33-12
1846V33-15
Parameter
READ CYCLE
Description
Min.
Max.
Min.
Max.
Unit
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
t
PD
WRITE CYCLE
[7]
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Shaded area contains advanced information.
Notes:
4.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
5.
At any given temperature and voltage condition, t
is less than t
for any given device. These parameters are guaranteed and not 100% tested.
6.
t
and t
are specified with C
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±
500 mV from steady-state voltage.
7.
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Read Cycle Time
12
15
ns
Address to Data Valid
12
15
ns
Data Hold from Address Change
3
3
ns
CS LOW to Data Valid
12
15
ns
OE LOW to Data Valid
7
8
ns
OE LOW to Low Z
0
0
ns
OE HIGH to High Z
CS LOW to Low Z
[5]
CS HIGH to High Z
[5, 6]
7
8
ns
3
3
ns
7
8
ns
CS HIGH to Power-Down
12
15
ns
Write Cycle Time
12
15
ns
CS LOW to Write End
9
10
ns
Address Set-Up to Write End
9
10
ns
Address Hold from Write End
0
0
ns
Address Set-Up to Write Start
1
1
ns
WE Pulse Width
10
12
ns
Data Set-Up to Write End
7
8
ns
Data Hold from Write End
1
1
ns
WE HIGH to Low Z
WE LOW to High Z
[6]
3
3
ns
0
7
0
8
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYM1846V33P8-12C | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:512K x 32 3.3V Static RAM Module |
| CYM1846V33P8-15C | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:512K x 32 3.3V Static RAM Module |
| CYM1846V33P8-20C | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:512K x 32 3.3V Static RAM Module |
| CYM1846V33P8-25C | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:512K x 32 3.3V Static RAM Module |
| CYM1846V33P8-35C | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:512K x 32 3.3V Static RAM Module |
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