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參數資料
| 型號： | CYM1836PY-15C |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 128K x 32 Static RAM Module |
| 中文描述： | 128K X 32 MULTI DEVICE SRAM MODULE, 15 ns, SMA64 |
| 封裝： | SIMM-64 |
| 文件頁數： | 4/8頁 |
| 文件大小： | 540K |
| 代理商： | CYM1836PY-15C |
CYM1836
4
Switching Characteristics
Over the Operating Range
[4]
Parameter
READ CYCLE
t
RC
t
AA
Description
1836–15
Min.
1836–20
Min.
1836–25
Min.
1836–30
Min.
1836–35
Min.
1836– 45
Min.
Unit
Max.
Max.
Max.
Max.
Max.
Max.
Read Cycle Time
Address to Data
Valid
Output Hold from
Address Change
CS LOW to Data
Valid
OE LOW to Data
Valid
OE LOW to
Low Z
OE HIGH to High
Z
CS LOW to
Low Z
[5]
CS HIGH to High
Z
[5, 6]
15
20
25
30
35
45
ns
ns
15
20
25
30
35
45
t
OHA
3
3
3
3
3
3
ns
t
ACS
15
20
25
30
35
45
ns
t
DOE
7
8
8
10
12
15
ns
t
LZOE
0
0
0
0
0
0
ns
t
HZOE
7
8
10
11
12
15
ns
t
LZCS
3
3
3
3
3
3
ns
t
HZCS
7
10
10
13
15
18
ns
WRITE CYCLE
[7]
t
WC
t
SCS
Write Cycle Time
CS LOW to Write
End
Address Set-Up
to Write End
Address Hold
from Write End
Address Set-Up
to Write Start
WE Pulse Width
Data Set-Up to
Write End
Data Hold from
Write End
WE HIGH to Low
Z
WE LOW to High
Z
[6]
15
12
20
15
25
15
30
18
35
20
45
25
ns
ns
t
AW
12
15
15
18
20
25
ns
t
HA
0
0
0
0
0
0
ns
t
SA
0
0
0
0
0
0
ns
t
PWE
t
SD
12
7
15
10
15
10
18
13
20
15
25
20
ns
ns
t
HD
0
0
0
0
0
0
ns
t
LZWE
3
3
3
3
3
3
ns
t
HZWE
0
6
0
8
0
10
0
15
0
15
0
18
ns
Shaded area contains preliminary information.
Notes:
4.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
At any given temperature and voltage condition, t
is less than t
for any given device. These parameters are guaranteed by design and not 100% tested.
t
and t
are specified with C
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±
500 mV from steady-state voltage.
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
5.
6.
7.
相關PDF資料 |
PDF描述 |
|---|---|
| CYM1836PY-20C | 128K x 32 Static RAM Module |
| CYM1836PY-25C | 128K x 32 Static RAM Module |
| CYM1836PY-30C | 128K x 32 Static RAM Module |
| CYM1836PY-35C | 128K x 32 Static RAM Module |
| CYM1836PY-45C | 128K x 32 Static RAM Module |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CYM1836PY-20C | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:128K x 32 Static RAM Module |
| CYM1836PY-25C | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:128K x 32 Static RAM Module |
| CYM1836PY-30C | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:128K x 32 Static RAM Module |
| CYM1836PY-35C | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:128K x 32 Static RAM Module |
| CYM1836PY-45C | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:128K x 32 Static RAM Module |
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