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參數(shù)資料
| 型號(hào)： | CYK001M16SCCA |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16-Mbit (1M x 16) Pseudo Static RAM |
| 中文描述： | 16兆位（1米× 16）偽靜態(tài)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大小： | 189K |
| 代理商： | CYK001M16SCCA |
16-Mbit (1M x 16) Pseudo Static RAM
CYK001M16SCCA
MoBL
Cypress Semiconductor Corporation
Document #: 38-05426 Rev. *D
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 26, 2005
Features
Advanced low-power MoBL
architecture
High speed: 55 ns, 70 ns
Wide voltage range: 2.7V to 3.3V
Typical active current: 3 mA @ f = 1 MHz
Typical active current: 13 mA @ f = f
MAX
Low standby power
Automatic power-down when deselected
Functional Description
[1]
The CYK001M16SCCA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 1M words by 16 bits that
supports an asynchronous memory interface. This device
features advanced circuit design to provide ultra-low active
current. This is ideal for providing More Battery Life
(MoBL)
in portable applications such as cellular telephones. The
device can be put into standby mode, reducing power
consumption dramatically when deselected (CE
1
LOW, CE
2
HIGH or both BHE and BLE are HIGH). The input/output pins
(I/O
0
through I/O
15
) are placed in a high-impedance state
when the chip is deselected (CE
1
HIGH, CE
2
LOW) or OE is
deasserted HIGH, or during a write operation (Chip Enabled
and Write Enable WE LOW). Reading from the device is
accomplished by asserting the Chip Enables (CE
1
LOW and
CE
2
HIGH) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the Truth Table for a complete description of read and write
modes.
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
1M x 16
RAM Array
I/O
0
–I/O
7
COLUMN DECODER
S
DATA IN DRIVERS
OE
BLE
I/O
8
–I/O
15
WE
BHE
R
Power
-
Down
Circuit
BHE
BLE
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
1
A
1
A
1
A
1
A
1
A
1
CE
2
CE
1
CE
2
CE
1
Logic Block Diagram
A
1
A
1
A
1
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相關(guān)代理商/技術(shù)參數(shù) |
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