- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379099 > CYIS1SM1000AA-HQC (Cypress Semiconductor Corp.) 1M Pixel Radiation Hard CMOS Image Sensor PDF資料下載
參數(shù)資料
| 型號： | CYIS1SM1000AA-HQC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1M Pixel Radiation Hard CMOS Image Sensor |
| 中文描述： | 輻射硬盤100萬像素CMOS圖像傳感器 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 611K |
| 代理商： | CYIS1SM1000AA-HQC |
STAR1000
Document Number: 38-05714 Rev. *B
Page 10 of 21
Pixel Read Out Timing
Figure 6. shows the timing of the pixel readout sequence. The
external digital controller presents a column address that is
latched by the rising edge of the LD_X pulse. After decoding
the X- address the column selection is clocked in the X-
register by CLK-X. The output amplifier uses the same pulse
to subtract the pixel output level from the pixel reset level and
the signal level. This causes a pipeline effect such that the
analog output of the first pixel is effectively present at the
device output terminal at the third rising edge of the X-CLK
signal.
The ADC conversion starts at the falling edge of the CLK-ADC
signal and produces a valid digital output 20 ns after this edge.
The timing constraints are given in Table 7.
Important note:
The values of the X shift-register tend to leak
away after a while. Therefore it is very important to keep the
CLK_X signal asserted for as long as the sensor is powered
up. If the sensor sits idle and CLK_X is not asserted, the
leakage of the X shift-register will cause multiple columns to
be selected at once. This forces high current through the
sensor and may cause damage.
Table 6. Timing Constraints of Line Sequence
Symbol
Min
Typ
Description
a
3.6
μ
s
Delay between selection of a new row and falling edge on S.
Minimal value: For maximum, speed a new row can already be selected
during X- read out of the previous row.
b
0.4
μ
s
Duration of S and R pulse.
c
0
100 ns
Delay between falling edge of S and rising edge of reset.
d
200 ns
Minimum duration of reset pulse.
e
1.6
μ
s
Delay between falling edge of reset and falling edge of R.
f
0
100 ns
Minimum delay between falling edge on LD_Y and rising edge of reset.
g
g
Minimum required extension of Y- address after falling edge of reset pulse.
h
100 ns
200 ns
Position of cal pulse after rising edge of S.
The cal pulse must only be given once per frame.
i
100 ns
1
μ
s
Duration of cal pulse.
k
10 ns
Address set up time.
l
20 ns
Load register value.
m
10 ns
Address stable after load.
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYK256K16MCBU-55BVXI | 4-Mbit (256K x 16) Pseudo Static RAM |
| CYK256K16MCBU-70BVXI | 4-Mbit (256K x 16) Pseudo Static RAM |
| CYK256K16MCCB | 4-Mbit (256K x 16) Pseudo Static RAM |
| CYK256K16MCCBU-55BVI | 4-Mbit (256K x 16) Pseudo Static RAM |
| CYK256K16MCCBU-60BVI | 4-Mbit (256K x 16) Pseudo Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYIS1SM1000-EVAL | 功能描述:光學(xué)傳感器開發(fā)工具 1M Pixel Radiation Hard CMOS Img Snsr RoHS:否 制造商:ams 工具用于評估: 接口類型: 最大工作溫度: |
| CYISM530AYXB | 功能描述:時鐘緩沖器 Reduction SSCGs COM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CYISM530AYXBT | 功能描述:時鐘緩沖器 Reduction SSCGs COM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CYISM530AZXC | 功能描述:時鐘緩沖器 Reduction SSCGs COM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CYISM530AZXCT | 功能描述:時鐘緩沖器 Reduction SSCGs COM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。