參數(shù)資料
型號: CYII4SM1300AA-QDC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 圖像傳感器
英文描述: 1.3 MPxl Rolling Shutter CMOS Image Sensor
中文描述: IMAGE SENSOR-CMOS, 1280(H) X 1024(V) PIXEL, 23fps, SQUARE, SURFACE MOUNT
封裝: 0.71 MM HEIGHT, 0.04 INCH PITCH, CERAMIC, LCC-84
文件頁數(shù): 12/37頁
文件大小: 1168K
代理商: CYII4SM1300AA-QDC
IBIS4-1300
Document Number: 38-05707 Rev. *B
Page 12 of 37
Figure 6. output amplifier architecture
Figure 6. shows the architecture of the output amplifier. First
of all, there is a multiplexer which selects either the imager
core signal or an external pin EXTIN as the input of the
amplifier. EXTIN can be used for evaluation, or to feed
alternative data to the output.
SEL_EXTIN controls this switch.
Then, the signal is fed to the first amplifier stage. This stage
has an adjustable gain, controlled by a 4-bit word
('gc_bit0...3').
Then, the upper level of the signal must be clipped in some
situations (clipping sometimes is necessary when the imager
signal is highly saturated, which affects the calibration level.
This is visible as black banding at the right side of bright
objects in the scene). In order to do this, a voltage should be
applied to the 'Clip' pin. The signal is clipped if it is higher than
Vclip - Vth,pmos, where Vth,pmos is the PMOS threshold
voltage and is typically -1 V. If clipping is not necessary, 5 V
should be applied to 'Clip'.
After this, the offset level is added. This offset level is set by a
DAC, controlled by a 4-bit word (DAC_bit0...3). The offset level
can be calibrated in two modes: fast offset adjustment or slow
offset adjustment. This is controlled by 'calib_s' and 'calib_f'.
The slow adjustment yields a somewhat cleaner image.
After this, the signal is buffered by a unity feedback amplifier
and it leaves the chip. This 2nd amplifier stage determines the
maximal readout speed, i.e. the bandwidth and the slew rate
of the output signal. The whole amplifier chain is designed for
a data rate of 10 Mpix/s (@ 40 pF). (It is up to the experimenter
to increase this speed by reducing the various setting
resistors)
Table 4. shows the IBIS4-1300 pins used by the output
amplifier with a short functional description. Power and ground
lines are shared between the output amplifier and the image
sensor.
Output amplifier offset level adjustment
The purpose of this adjustment is to bring the pixel voltage
range as good as possible within the ADC range. The offset
level of the output signal is controlled by a 4-bit resistive DAC.
This DAC selects the offset level on a linear scale between 2
reference voltages. These reference voltages are applied to
Vlow_dac and Vhigh_dac.
This offset level is adjusted during the calibration phase.
During this phase, the amplifier input should be constant and
refers to the 'zero' signal situation. The IBIS4-1300 outputs a
dark reference signal after a row has been read out
completely. This signal can be used as the 'zero signal'
reference. Alternatively one can apply an external reference
on pin EXTIN, which is applied to the output amplifier when
SEL_EXTIN is 1.
Offset adjustment can be done during row or frame blanking
time.
Calib_f
A
1
+
sel_extin
extin
pixel array
gain [0..3]
unity gain
offset [0..3]
D
A
C
Vhigh_dac
Vlow_dac
Calib_s
Clip
1.1.1.1.1
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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