參數(shù)資料
型號： CYDC064B08-55AXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM
中文描述： 8K X 8 DUAL-PORT SRAM, 55 ns, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, TQFP-100
文件頁數(shù)： 13/26頁
文件大?。?/td> 580K
代理商： CYDC064B08-55AXC
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *E
Page 13 of 26
7
AC Test Loads and Waveforms
Switching Characteristics for V
CC
= 1.8V
Over the Operating Range
[27]
Parameter
Description
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08,
CYDC064B08
Unit
-40
-55
Min.
Max.
Min.
Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE[28]
t
DOE
t
LZOE[29, 30, 31]
t
HZOE[29, 30, 31]
t
LZCE[29, 30, 31]
t
HZCE[29, 30, 31]
t
PU[31]
t
PD[31]
t
ABE[28]
Write Cycle
Read Cycle Time
40
55
ns
Address to Data Valid
40
55
ns
Output Hold From Address Change
5
5
ns
CE LOW to Data Valid
40
55
ns
OE LOW to Data Valid
25
30
ns
OE Low to Low Z
5
5
ns
OE HIGH to High Z
15
25
ns
CE LOW to Low Z
5
5
ns
CE HIGH to High Z
15
25
ns
CE LOW to Power-Up
0
0
ns
CE HIGH to Power-Down
40
55
ns
Byte Enable Access Time
40
55
ns
t
WC
t
SCE[28]
t
AW
Write Cycle Time
40
55
ns
CE LOW to Write End
30
45
ns
Address Valid to Write End
30
45
ns
Notes:
27.Test conditions assume signal transition time of 3 ns or less, timing reference levels of V
CC
/2, input pulse levels of 0 to V
CC
, and output loading of the specified
I
/I
and 30-pF load capacitance.
28.To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
SCE
time.
29.At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
30.Test conditions used are Load 3.
31.This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with
Busy waveform
1.8V
GND
90%
90%
10%
10%
ALL INPUT PULSES
(a) Normal Load (Load 1)
R1
3.0V/2.5V/1.8V
OUTPUT
R2
C = 30 pF
V
TH
= 0.8V
OUTPUT
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 2)
(Used for t
LZ
, t
HZ
, t
HZWE
, and t
LZWE
R1
R2
3.0V/2.5V/1.8V
OUTPUT
R
TH
= 6 k
≤
3 ns
≤
3 ns
including scope and jig)
3.0V/2.5V
1022
792
1.8V
13500
10800
R1
R2
C = 30 pF
C = 5 pF
[+] Feedback
相關(guān)PDF資料
PDF描述
CYDC064B08-55AXI 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM
CYDC064B16 Replacement for National Semiconductor part number DM9328N. Buy from authorized manufacturer Rochester Electronics.
CYDC064B16-40AXC 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM
CYDC064B16-55AXC Replacement for National Semiconductor part number DM9334J. Buy from authorized manufacturer Rochester Electronics.
CYDC064B16-55AXI 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYDC064B08-55AXI 功能描述:靜態(tài)隨機存取存儲器 64K 8Kx8 Consumer Hi Vol Dual Port IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CYDC064B16 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM
CYDC064B16-40AXC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM
CYDC064B16-55AXC 制造商:Cypress Semiconductor 功能描述:
CYDC064B16-55AXI 功能描述:靜態(tài)隨機存取存儲器 64K 4Kx16 Consumer Hi Vol Dual Port IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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