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參數(shù)資料
| 型號： | CYD18S72V-100BBC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM |
| 中文描述： | 256K X 72 DUAL-PORT SRAM, 5.2 ns, PBGA484 |
| 封裝： | 23 X 23 MM, 1 MM, ROHS COMPLIANT, MO-192, FBGA-484 |
| 文件頁數(shù)： | 5/26頁 |
| 文件大?。?/td> | 470K |
| 代理商： | CYD18S72V-100BBC |
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PRELIMINARY
CYD04S72V
CYD09S72V
CYD18S72V
Document #: 38-06069 Rev. *D
Page 5 of 26
Master Reset
The FLEx72 family devices undergo a complete reset by
taking the MRST input LOW. MRST input can switch
asynchronously to the clocks. MRST initializes the internal
burst counters to zero, and the counter mask registers to all
ones (completely unmasked). MRST also forces the mailbox
interrupt (INT) flags and the Counter Interrupt (CNTINT) flags
HIGH. MRST must be performed on the FLEx72 family
devices after power-up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports.
Table 2
shows the interrupt operation for both ports using 18Mbit
device as an example. The highest memory location, 3FFFF
is the mailbox for the right port and 3FFFE is the mailbox for
the left port.
Table 2.
shows that in order to set the INT
R
flag, a
Table 2. Interrupt Operation Example
[1, 11, 12, 13]
write operation by the left port to address 3FFFF will assert
INT
R
LOW. At least one byte has to be active for a write to
generate an interrupt. A valid Read of the 3FFFF location by
the right port will reset INT
R
HIGH. At least one byte has to be
active in order for a read to reset the interrupt. When one port
writes to the other port’s mailbox, the INT of the port that the
mailbox belongs to is asserted LOW.
The INT is reset when the owner (port) of the mailbox reads
the contents of the mailbox. The interrupt flag is set in
a flow-thru mode (i.e., it follows the clock edge of the writing
port). Also, the flag is reset in a flow-thru mode (i.e., it follows
the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
TDI
JTAG Test Data Input
. Data on the TDI input will be shifted serially into selected
registers.
JTAG Test Clock Input
.
TCK
TDO
JTAG Test Data Output
. TDO transitions occur on the falling edge of TCK.
TDO is normally three-stated except when captured data is shifted out of the
JTAG TAP.
Ground Inputs
.
V
SS
V
CORE
Core Power Supply
.
V
TTL
LVTTL Power Supply
.
Pin Definitions
(continued)
Left Port
Right Port
Description
Function
Left Port
Right Port
R/W
L
L
CE
L
L
A
0
L
–17
L
3FFFF
INT
L
X
R/W
R
X
CE
R
X
A
0R–17R
X
INT
R
L
Set Right INT
R
Flag
Reset Right INT
R
Flag
X
X
X
X
H
L
3FFFF
H
Set Left INT
L
Flag
X
X
X
L
L
L
3FFFE
X
Reset Left INT
L
Flag
H
L
3FFFE
H
X
X
X
X
Note:
11.
CE is internal signal. CE = LOW if CE
= LOW and CE
= HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of
the CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
12. OE is “Don’t Care” for mailbox operation.
13. At least one of BE0 or BE7 must be LOW.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYD18S72V-100BBI | FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM |
| CYD18S72V-133BBC | FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM |
| CYD18S36V | FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM(FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36同步雙端口RAM) |
| CYD02S36V | FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM(FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36同步雙端口RAM) |
| CYD04S36V | FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM(FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36同步雙端口RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYD18S72V-100BBI | 功能描述:靜態(tài)隨機存取存儲器 18M (256Kx72) 3.3v 100MHz Synch 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYD18S72V-100BBXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FLEx72⑩ 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM |
| CYD18S72V-100BBXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FLEx72⑩ 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM |
| CYD18S72V-133BBC | 功能描述:靜態(tài)隨機存取存儲器 18M Sync Dual Port 256K x 72 3.3V COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYD18S72V-133BBI | 功能描述:靜態(tài)隨機存取存儲器 18M (256Kx72) 3.3v 133MHz Synch 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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