參數(shù)資料
型號: CY8CLED03D02-56LTXI
廠商: Cypress Semiconductor Corp
文件頁數(shù): 42/55頁
文件大?。?/td> 0K
描述: IC POWERPSOC 3CH 1A 56VQFN
特色產(chǎn)品: PowerPSoC? Embedded Power Controller
標(biāo)準(zhǔn)包裝: 260
系列: PowerPSoC® CY8CLED
核心處理器: M8C
芯體尺寸: 8-位
速度: 24MHz
連通性: DALI,DMX512,I²C,IrDA,SPI,UART/USART
外圍設(shè)備: LED,LVD,POR,PWM,WDT
輸入/輸出數(shù): 14
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.75 V ~ 5.25 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 56-VFQFN 裸露焊盤
包裝: 托盤
配用: 428-2882-ND - KIT STARTER POWERPSOC LIGHTING
428-2281-ND - KIT EVAL POWERPSOC LIGHTING
428-2270-ND - KIT STARTER DEMO LIGHTING
其它名稱: 428-2925
CY8CLED04D01, CY8CLED04D02, CY8CLED04G01
CY8CLED03D01, CY8CLED03D02, CY8CLED03G01
CY8CLED02D01, CY8CLED01D01
Document Number: 001-46319 Rev. *P
Page 47 of 55
15.17 PSoC Core POR and LVD
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PowerPSoC Technical Reference
Manual for more information on the VLT_CR register.
15.18 PSoC Core Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Table 15-31. POR and LVD DC Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VPPOR2
VDD Value for PPOR Trip
PORLEV[1:0] = 10b
4.55
4.70
V
VLVD6
VLVD7
VDD Value for LVD Trip
VM[2:0] = 110b
VM[2:0] = 111b
4.62
4.71
4.73
4.81
4.83
4.95
V
Table 15-32. Programming DC Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
IDDP
Supply current during programming or verify
15
30
mA
VILP
Input low voltage during programming or verify
0.8
V
VIHP
Input high voltage during programming or
verify
2.1
V
IILP
Input current when applying Vilp to P1[0] or
P1[1] during programming or verify
0.2
mA
Driving internal pull down
resistor.
IIHP
Input current when applying Vihp to P1[0] or
P1[1] during programming or verify
1.5
mA
Driving internal pull down
resistor.
VOLV
Output low voltage during programming or
verify
VSS + 0.75
V
VOHV
Output high voltage during programming or
verify
VDD – 1.0
VDD
V
FlashENPB Flash endurance (per block)
50,000
Erase/write cycles per
block.
FlashENT
Flash endurance (total)[16]
1,800,000
Erase/write cycles.
FlashDR
Flash data retention[17]
10
Years
Notes
16. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36 x 1 blocks of 50,000 maximum cycles each, 36 x 2
blocks of 25,000 maximum cycles each, or 36 x 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 x 50,000 and that no single block
ever sees more than 50,000 cycles)
17. Guaranteed for –40 °C
T
A 85 °C for Industrial rated devices and –40 °C TA 105 °C for Extended Temperature rated devices.
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