參數(shù)資料
型號: CY8C29666-24PVXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 外設(shè)及接口
英文描述: Mixed Signal Array
中文描述: MULTIFUNCTION PERIPHERAL, PDSO48
封裝: 0.300 INCH, LEAD FREE, SSOP-48
文件頁數(shù): 26/40頁
文件大?。?/td> 474K
代理商: CY8C29666-24PVXI
August 3, 2004
Document No. 38-12013 Rev. *F
26
CY8C29x66 Preliminary Data Sheet
3. Electrical Specifications
3.4
AC Electrical Characteristics
3.4.1
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
T
A
85
°
C, or 3.0V to 3.6V and -40
°
C
T
A
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
Note
See the individual user module data sheets for information on maximum frequencies for user modules.
Table 3-16: AC Chip-Level Specifications
Symbol
F
IMO24
Description
Min
Typ
Max
Units
MHz
Notes
Internal Main Oscillator Frequency for 24 MHz
23.4
24
24.6
a,b,c
Trimmed for 5V or 3.3V operation using
factory trim values. See Figure 3-1b on
page 17
. SLIMO Mode = 0.
Trimmed for 5V or 3.3V operation using
factory trim values. See Figure 3-1b on
page 17
. SLIMO Mode = 1.
F
IMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
6
6.35
a,b,c
MHz
F
CPU1
F
CPU2
F
48M
CPU Frequency (5V Nominal)
0.93
24
24.6
a,b
12.3
b,c
49.2
a,b,d
a. 4.75V < Vdd < 5.25V.
b. Accuracy derived fromInternal Main Oscillator with appropriate trimfor Vdd range.
c. 3.0V < Vdd < 3.6V.
d. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimmng for 3.3V operation.
MHz
CPU Frequency (3.3V Nominal)
0.93
12
MHz
Digital PSoC Block Frequency
0
48
MHz
Refer to the AC Digital Block Specifica-
tions below.
F
24M
F
32K1
F
32K2
Digital PSoC Block Frequency
0
24
24.6
b, d
64
MHz
Internal Low Speed Oscillator Frequency
15
32
kHz
External Crystal Oscillator
32.768
kHz
Accuracy is capacitor and crystal dependent.
50% duty cycle.
A multiple (x732) of crystal frequency.
F
PLL
Jitter24M2
T
PLLSLEW
T
PLLSLEWLOW
T
OS
T
OSACC
PLL Frequency
23.986
MHz
24 MHz Period Jitter (PLL)
PLL Lock Time
0.5
600
10
ps
ms
PLL Lock Time for Low Gain Setting
0.5
50
ms
External Crystal Oscillator Startup to 1%
250
500
ms
External Crystal Oscillator Startup to 100 ppm
300
600
ms
The crystal oscillator frequency is within 100 ppm
of its final value by the end of the T
osacc
period.
Correct operation assumes a properly loaded 1 uW
maximumdrive level 32.768 kHz crystal. 3.0V
Vdd
5.5V, -40
o
C
T
A
85
o
C.
Jitter32k
T
XRST
DC24M
Step24M
Fout48M
32 kHz Period Jitter
External Reset Pulse Width
10
100
ns
μ
s
%
kHz
MHz
24 MHz Duty Cycle
24 MHz Trim Step Size
48 MHz Output Frequency
40
46.8
50
50
48.0
60
49.2
a,c
Trimmed. Utilizing factory trim values.
Jitter24M1
F
MAX
T
RAMP
24 MHz Period Jitter (IMO)
Maximum frequency of signal on row input or row output.
600
ps
MHz
12.3
Supply Ramp Time
0
μ
s
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