參數(shù)資料
型號(hào)： CY8C29466-24PXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 外設(shè)及接口
英文描述： Mixed Signal Array
中文描述： MULTIFUNCTION PERIPHERAL, PDIP28
封裝： 0.300 INCH, LEAD FREE, MO-095, DIP-28
文件頁(yè)數(shù)： 32/40頁(yè)
文件大?。?/td> 474K
代理商： CY8C29466-24PXI
August 3, 2004
Document No. 38-12013 Rev. *F
32
CY8C29x66 Preliminary Data Sheet
3. Electrical Specifications
3.4.6
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
3.4.7
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
Table 3-23: 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
F
OSCEXT
Frequency
0.093
–
24.6
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
μ
s
–
Power Up IMO to Switch
150
–
–
Table 3-24: 3.3V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
F
OSCEXT
Frequency with CPU Clock divide by 1
0.093
–
12.3
MHz
Maximum CPU frequency is 12 MHz at 3.3V.
With the CPU clock divider set to 1, the
external clock must adhere to the maximum
frequency and duty cycle requirements.
F
OSCEXT
Frequency with CPU Clock divide by 2 or greater
0.186
–
24.6
MHz
If the frequency of the external clock is
greater than 12 MHz, the CPU clock divider
must be set to 2 or greater. In this case, the
CPU clock divider will ensure that the fifty
percent duty cycle requirement is met.
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
μ
s
–
Power Up IMO to Switch
150
–
–
Table 3-25: AC Programming Specifications
Symbol
T
RSCLK
T
FSCLK
T
SSCLK
T
HSCLK
F
SCLK
T
ERASEB
T
WRITE
T
DSCLK
T
DSCLK3
Description
Min
Typ
Max
Units
ns
Notes
Rise Time of SCLK
1
–
20
Fall Time of SCLK
1
–
20
ns
Data Set up Time to Falling Edge of SCLK
40
–
–
ns
Data Hold Time from Falling Edge of SCLK
40
–
–
ns
Frequency of SCLK
0
–
8
MHz
Flash Erase Time (Block)
–
10
–
ms
Flash Block Write Time
–
10
–
ms
Data Out Delay from Falling Edge of SCLK
–
–
45
ns
Vdd
>
3.6
3.0
≤
Vdd
≤
3.6
Data Out Delay from Falling Edge of SCLK
–
–
50
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY8C29466-24SXI 功能描述:可編程片上系統(tǒng) - PSoC IC MCU 32K FLASH 2K SRAM RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT
CY8C29466-24SXIT 功能描述:可編程片上系統(tǒng) - PSoC 32K Flsh 2KB RAM IND RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT
CY8C294664-24PVXI 功能描述:PROGRAMMABLE SYSTEM ON A CHIP RoHS:是 類別:未定義的類別 >> 其它 系列:* 標(biāo)準(zhǔn)包裝:1 系列:* 其它名稱:MS305720A
CY8C294665-24PVXI 制造商:Cypress Semiconductor 功能描述:
CY8C29566-24AXI 功能描述:可編程片上系統(tǒng) - PSoC IC MCU 32K FLASH 2K SRAM RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT
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