參數(shù)資料
型號： CY8C29466-24PVXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 外設(shè)及接口
英文描述： Mixed Signal Array
中文描述： MULTIFUNCTION PERIPHERAL, PDSO28
封裝： 0.210 INCH, LEAD FREE, SSOP-28
文件頁數(shù)： 22/40頁
文件大小： 474K
代理商： CY8C29466-24PVXI
August 3, 2004
Document No. 38-12013 Rev. *F
22
CY8C29x66 Preliminary Data Sheet
3. Electrical Specifications
3.3.5
DC Switch Mode Pump Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
Figure 3-2. Basic Switch Mode Pump Circuit
I
SOB
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio
–
60
0.8
2.0
–
1
5
–
mA
mA
dB
PSRR
OB
Table 3-10: DC Switch Mode Pump (SMP) Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
V
PUMP
5V
5V Output Voltage at Vdd from Pump
4.75
5.0
5.25
V
Configuration of footnote
a
. Average, neglecting ripple. SMP
trip voltage is set to 5.0V.
a. L
1
= 2
μ
H inductor, C
1
= 10
μ
F capacitor, D
1
= Schottky diode. See Figure3-2.
V
PUMP
3V
3V Output Voltage at Vdd from Pump
3.00
3.25
3.60
V
Configuration of footnote
a
. Average, neglecting ripple. SMP
trip voltage is set to 3.25V.
I
PUMP
Available Output Current
V
BAT
= 1.5V, V
PUMP
= 3.25V
V
BAT
= 1.8V, V
PUMP
= 5.0V
8
5
–
–
–
–
mA
mA
Configuration of footnote
a
.
SMP trip voltage is set to 3.25V.
SMP trip voltage is set to 5.0V.
V
BAT
5V
Input Voltage Range from Battery
1.8
–
5.0
V
Configuration of footnote
a
. SMP trip voltage is set to 5.0V.
V
BAT
3V
Input Voltage Range from Battery
1.0
–
3.3
V
Configuration of footnote
a
. SMP trip voltage is set to 3.25V.
V
BATSTART
Minimum Input Voltage from Battery to
Start Pump
1.2
–
–
V
Configuration of footnote
a
. 0
o
C
≤
T
A
≤
100. 1.25V at T
A
= -
40
o
C.
V
PUMP_Line
Line Regulation (over V
BAT
range)
–
5
–
%V
O
Configuration of footnote
a
. V
O
is the “Vdd Value for PUMP
Trip” specified by the VM[2:0] setting in the DC POR and
LVD Specification,
Table 3-14 on page 24
.
V
PUMP_Load
Load Regulation
–
5
–
%V
O
Configuration of footnote
a
. V
O
is the “Vdd Value for PUMP
Trip” specified by the VM[2:0] setting in the DC POR and
LVD Specification,
Table 3-14 on page 24
.
V
PUMP_Ripple
Output Voltage Ripple (depends on capaci-
tor/load)
–
100
–
mVpp
Configuration of footnote
a
. Load is 5 mA.
E
3
Efficiency
35
50
–
%
Configuration of footnote
a
. Load is 5 mA. SMP trip voltage
is set to 3.25V.
F
PUMP
Switching Frequency
–
1.4
–
MHz
DC
PUMP
Switching Duty Cycle
–
50
–
%
Table 3-9: 3.3V DC Analog Output Buffer Specifications
(continued)
Battery
C1
D1
+
PSoC
TM
Vdd
Vss
SMP
V
BAT
V
PUMP
L
1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY8C29466-24PVXIES 制造商:Cypress Semiconductor 功能描述:
CY8C29466-24PVXIT 功能描述:可編程片上系統(tǒng) - PSoC 24 I/O 32K Flash 2K bytes RAM RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:67 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT
CY8C29466-24PXI 功能描述:可編程片上系統(tǒng) - PSoC IC MCU 32K FLASH 2K SRAM RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:67 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT
CY8C29466-24SXI 功能描述:可編程片上系統(tǒng) - PSoC IC MCU 32K FLASH 2K SRAM RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:67 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT
CY8C29466-24SXIT 功能描述:可編程片上系統(tǒng) - PSoC 32K Flsh 2KB RAM IND RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:67 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT
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