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      參數(shù)資料
      

      


      


      
型號(hào)：
CY8C27643-24LFXI

      

      
廠商：
CYPRESS SEMICONDUCTOR CORP

      

      
元件分類(lèi)：
外設(shè)及接口

      

      
英文描述：
PSoC Mixed Signal Array

      

      
中文描述：
MULTIFUNCTION PERIPHERAL, QCC48

      

      
封裝：
7 X 7 MM, LEAD FREE, MO-220, QFN-48

      

      
文件頁(yè)數(shù)：
24/44頁(yè)

      

      
文件大?。?/td>
542K

      

      
代理商：
CY8C27643-24LFXI


      

      

      

	
      
    
    

    
      
	
      August 3, 2004
      Document No. 38-12012 Rev. *I
      24
      CY8C27x43 Final Data Sheet
      3.  Electrical Specifications
      3.3.6
      DC Analog Reference Specifications
      The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
      and -40
      °
      C 
      ≤
       T
      A
      ≤
       85
      °
      C, or 3.0V to 3.6V and -40
      °
      C 
      ≤
       T
      A
      ≤
       85
      °
      C, respectively. Typical parameters apply to 5V and 3.3V at 25
      °
      C and
      are for design guidance only.
      The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
      the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
      register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
      Reference control power is high. 
      Table 3-11. Silicon Revision A – 5V DC Analog Reference Specifications
      Symbol
      BG
      –
      Description
      Min
      Typ
      Max
      Units
      Bandgap Voltage Reference
      AGND = Vdd/2
      a
      AGND = 2 x BandGap
      a
      AGND = P2[4] (P2[4] = Vdd/2)
      a
      AGND = BandGap
      a
      AGND = 1.6 x BandGap
      a
      AGND Block to Block Variation (AGND = Vdd/2)
      a
      RefHi = Vdd/2 + BandGap
      1.274
      Vdd/2 - 0.030
      1.30
      Vdd/2 - 0.004
      1.326
      Vdd/2 + 0.003
      V
      V
      a. AGND tolerance includes the offsets of the local buffer in the PSoC block.
      –
      2 x BG - 0.043
      2 x BG - 0.010
      2 x BG + 0.024
      V
      –
      P2[4] - 0.013
      P2[4]
      P2[4] + 0.014
      V
      –
      BG - 0.009
      BG
      BG + 0.009
      V
      –
      1.6 x BG - 0.018
      1.6 x BG
      1.6 x BG + 0.018
      V
      –
      -0.034
      0.000
      0.034
      V
      –
      Vdd
      /2 + BG - 0.140
      3 x BG - 0.112
      2 x BG + P2[6] - 0.113
      P2[4] + BG - 0.130
      P2[4] + P2[6] - 0.133
      3.2 x BG - 0.112
      Vdd
      /2 - BG - 0.051
      BG - 0.082
      2 x BG - P2[6] - 0.084
      P2[4] - BG - 0.056
      P2[4] - P2[6] - 0.057
      Vdd
      /2 + BG - 0.018
      3 x BG - 0.018
      2 x BG + P2[6] - 0.018
      P2[4] + BG - 0.016
      P2[4] + P2[6] - 0.016
      3.2 x BG
      Vdd
      /2 - BG 
      + 
      0.024
      BG + 0.023
      2 x BG - P2[6] + 0.025
      P2[4] - BG + 0.026
      P2[4] - P2[6] + 0.026
      Vdd
      /2 + BG + 0.103
      3 x BG + 0.076
      2 x BG + P2[6] + 0.077
      P2[4] + BG + 0.098
      P2[4] + P2[6] + 0.100
      3.2 x BG + 0.076
      Vdd
      /2 - BG + 0.098
      BG + 0.129
      2 x BG - P2[6] + 0.134
      P2[4] - BG + 0.107
      P2[4] - P2[6] + 0.110
      V
      –
      –
      –
      –
      –
      –
      RefHi = 3 x BandGap
      RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
      RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
      RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
      RefHi = 3.2 x BandGap
      RefLo = Vdd/2 – BandGap
      V
      V
      V
      V
      V
      V
      –
      –
      –
      –
      RefLo = BandGap
      RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
      RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
      RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
      V
      V
      V
      V
      Table 3-12. Silicon Revision B – 5V DC Analog Reference Specifications
      Symbol
      BG
      –
      Description
      Min
      Typ
      Max
      Units
      Bandgap Voltage Reference
      AGND = Vdd/2
      a
      AGND = 2 x BandGap
      a
      AGND = P2[4] (P2[4] = Vdd/2)
      a
      AGND = BandGap
      a
      AGND = 1.6 x BandGap
      a
      AGND Block to Block Variation (AGND = Vdd/2)
      a
      RefHi = Vdd/2 + BandGap
      1.28
      Vdd/2 - 0.030
      1.30
      Vdd/2
      1.32
      Vdd/2 + 0.007
      V
      V
      a. AGND tolerance includes the offsets of the local buffer in the PSoC block.
      –
      2 x BG - 0.043
      2 x BG
      2 x BG + 0.024
      V
      –
      P2[4] - 0.011
      P2[4]
      P2[4] + 0.011
      V
      –
      BG - 0.009
      BG
      BG + 0.009
      V
      –
      1.6 x BG - 0.018
      1.6 x BG
      1.6 x BG + 0.018
      V
      –
      -0.034
      0.000
      0.034
      V
      –
      Vdd
      /2 + BG - 0.1
      3 x BG - 0.06
      2 x BG + P2[6] - 0.06
      P2[4] + BG - 0.06
      P2[4] + P2[6] - 0.06
      3.2 x BG - 0.06
      Vdd
      /2 - BG - 0.051
      BG - 0.06
      2 x BG - P2[6] - 0.04
      P2[4] - BG - 0.056
      P2[4] - P2[6] - 0.056
      Vdd
      /2 + BG - 0.01
      3 x BG - 0.01
      2 x BG + P2[6] - 0.01
      P2[4] + BG - 0.01
      P2[4] + P2[6] - 0.01
      3.2 x BG - 0.01
      Vdd
      /2 - BG 
      + 
      0.01
      BG + 0.01
      2 x BG - P2[6] + 0.01
      P2[4] - BG + 0.01
      P2[4] - P2[6] + 0.01
      Vdd
      /2 + BG + 0.1
      3 x BG + 0.06
      2 x BG + P2[6] + 0.06
      P2[4] + BG + 0.06
      P2[4] + P2[6] + 0.06
      3.2 x BG + 0.06
      Vdd
      /2 - BG + 0.06
      BG + 0.06
      2 x BG - P2[6] + 0.04
      P2[4] - BG + 0.056
      P2[4] - P2[6] + 0.056
      V
      –
      –
      –
      –
      –
      –
      RefHi = 3 x BandGap
      RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
      RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
      RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
      RefHi = 3.2 x BandGap
      RefLo = Vdd/2 – BandGap
      V
      V
      V
      V
      V
      V
      –
      –
      –
      –
      RefLo = BandGap
      RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
      RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
      RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
      V
      V
      V
      V
      
    
      
    
    
      


      


      

      相關(guān)PDF資料
      		

      PDF描述
      		

      
      

      
CY8C27643-24LFXIT
PSoC Mixed Signal Array

      

      
CY8C27643-24PVI
PSoC Mixed Signal Array

      

      
CY8C27643-24PVIT
PSoC Mixed Signal Array

      

      
CY8C27643-24PVXI
PSoC Mixed Signal Array

      

      
CY8C27643-24PVXIT
PSoC Mixed Signal Array

      

      

      

      


      


      

      相關(guān)代理商/技術(shù)參數(shù)
      		

      參數(shù)描述
      		

      
      

      
CY8C27643-24LFXIT
功能描述:可編程片上系統(tǒng) - PSoC 16K FlSh 256B RAM IND RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT

      

      
CY8C27643-24LTXI
功能描述:可編程片上系統(tǒng) - PSoC 16 KB 256 B RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT

      

      
CY8C27643-24LTXIT
功能描述:可編程片上系統(tǒng) - PSoC 16 KB 256 B RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT

      

      
CY8C27643-24PVIT
功能描述:IC MCU 16K FLASH 256B 48-SSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C27xxx 產(chǎn)品培訓(xùn)模塊:The Ultra-Low Power MSP430
	MSP430 Overview
	MSP430 Design Tools
	MSP430 Peripherals
	MSP430x2xx/4xx and Wireless Overview
	Portable Medical Solutions with MSP430
	MSP430 for Utility Metering Solutions
	MSP430: How to JTAG
	MSP430, How To Use the Clock System
	Grace Software Graphical User Interface
	MCU Overview
	Driver Library
	MSP430Ware Overview 標(biāo)準(zhǔn)包裝:1 系列:MSP430x4xx 核心處理器:RISC 芯體尺寸:16-位 速度:8MHz 連通性:SPI，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，LCD，POR，PWM，WDT 輸入/輸出數(shù):48 程序存儲(chǔ)器容量:32KB（32K x 8 + 256B） 程序存儲(chǔ)器類(lèi)型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):1.8 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 包裝:Digi-Reel® 其它名稱(chēng):296-26232-6

      

      
CY8C27643-24PVXI
功能描述:可編程片上系統(tǒng) - PSoC IC MCU 16K FLSH 256B SRAM RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT

      

      
    
    
    
	
      	
    
    
     
     
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