參數(shù)資料
型號: CY8C24794-SPPVX
廠商: Cypress Semiconductor Corp.
英文描述: Environmentally sealed limit switch with Leadwire termination, Rotary Roller Lever actuation, Double Pole Double Throw (DPDT) Circuitry, 5 A (Resistive) ampere rating at 28 Vdc, Military Part Number MS21320-2
中文描述: PSoCTM混合信號陣列
文件頁數(shù): 8/32頁
文件大?。?/td> 366K
代理商: CY8C24794-SPPVX
April 14, 2005
Document No. 38-12018 Rev. *F
8
1.
Pin Information
This chapter describes, lists, and illustrates the CY8C24794 PSoC device pins and pinout configuration.
1.1
56-Pin Part Pinout
The CY8C24794 PSoC device is available in a 56-pin package which is listed and illustrated in the following table. Every port pin
(labeled with a “P”) is capable of Digital IO. However, Vss and Vdd are not capable of Digital IO.
Table 1-1. 56-Pin Part Pinout (MLF
*
)
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Type
Name
Description
CY8C24794 56-Pin PSoC Device
Digital Analog
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Power
USB
USB
Power
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I, M
I, M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
D+
D-
Vdd
P7[7]
P7[0]
P1[0]
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
P4[0]
P4[2]
P4[4]
Direct switched capacitor block input.
Direct switched capacitor block input.
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
I2C Serial Clock (SCL), ISSP-SCLK.
Ground connection.
Supply voltage.
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
I2C Serial Data (SDA), ISSP-SDATA.
Pin
No.
44
45
46
47
48
49
50
51
52
Type
Name
Description
Digital Analog
IO
IO
IO
IO
IO
Power
Power
IO
IO
M
I, M
I, M
I, M
I, M
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Vss
P0[7]
P0[5]
External Voltage Reference (VREF) input.
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
Ground connection.
Analog column mux input, integration input #1.
Analog column mux input and column output,
integration input #2.
Analog column mux input and column output.
Analog column mux input.
I, M
IO, M
40
41
42
43
IO
IO
IO
IO
M
I, M
I, M
M
P4[6]
P2[0]
P2[2]
P2[4]
53
54
55
56
IO
IO
IO
IO
IO, M
I, M
M
M
P0[3]
P0[1]
P2[7]
P2[5]
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND) input.
LEGEND
A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* The MLF package has a center pad that must be connected to ground (Vss).
MLF
(Top View)
A, I, M, P2[3]
A, I, M, P2[1]
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
M
M
M
M
V
D
D
V
P
P
M
M
M
M
1
1
1
1
1
2
2
2
2
2
2
2
2
2
P
P
P
P
P
P
V
V
P
P
P
P
P
P
4
4
4
4
4
4
4
5
5
5
5
5
5
5
P2[2], A, I, M
P2[0], A, I, M
P4[6], M
P4[4], M
P4[2], M
P4[0], M
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
42
41
40
39
38
37
36
35
34
33
32
31
30
29
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