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| 型號(hào)： | CY8C22213-24PI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | PSoC Mixed Signal Array |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PDIP20 |
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17. Digital Blocks
CY8C22xxx Preliminary Data Sheet
192
Document No. 38-12009 Rev. *D
December 22, 2003
17.1.5
Timer Function
A timer consists of a period register, a synchronous down
counter, and a capture/compare register, all of which are
byte wide. When the timer is disabled and a period value is
written into DR1, the period value is also loaded into DR0.
When the timer is enabled, the counter counts down until
positive terminal count (a count of 00h) is reached. On the
next clock edge, the period is reloaded and on subsequent
clocks counting continues. The terminal count signal is the
primary function output.
Hardware capture occurs on the positive edge of the data
input. This event transfers the current count from DR0 to
DR2. The captured value may then be read directly from
DR2. A software capture function is equivalent to a hard-
ware capture. A CPU read of DR0, with the timer enabled,
triggers the same capture mechanism. The hardware and
software capture mechanisms are OR’ed in the capture cir-
cuitry. Since the capture circuitry is positive edge sensitive,
during an interval where the hardware capture input is high,
a software capture is masked and will not occur.
The Timer also implements a compare function between
DR0 and DR2. The compare signal is the auxiliary function
output. A limitation, in regards to the compare function, is
that the capture and compare function both use the same
register (DR2). Therefore, if a capture event occurs, it will
overwrite the compare value.
Mode bit 1 in the Function register sets the compare type
(DR0 <= DR2 or DR0 < DR2) and Mode bit 0 sets the inter-
rupt type (Terminal Count or Compare).
Timers may be chained in 8-bit lengths up to 32 bits.
17.1.5.1
Usability Exceptions
The following are usability exceptions for the Timer function.
1.
Capture operation is not supported at 48 MHz.
2.
DR2 is not writeable when the Timer is enabled.
17.1.5.2
Block Interrupt
The Timer block has a selection of three interrupt sources.
Interrupt on Terminal Count (TC) and Compare may be
selected in Mode bit 0 of the Function register. The interrupt
on Capture may be selected with the Capture Interrupt bit in
the Control register.
Interrupt on Terminal Count: The positive edge of Termi-
nal Count (primary output) generates an interrupt for this
block. The timing of the interrupt follows the TC Pulse
Width setting in the Control register.
I
Interrupt on Compare: The positive edge of Compare
(auxiliary output) generates an interrupt for this block.
I
Interrupt on Capture: Hardware or software capture gen-
erates an interrupt for this block. The interrupt occurs at
closing of the DR2 latch on capture.
I
17.1.6
Counter Function
A Counter consists of a period register, a synchronous down
counter, and a compare register. The Counter function is
identical to the Timer function except for the following points:
The Data input is a counter gate (enable), rather than a
capture input. Counters do not implement synchronous
capture. The DR0 register in a counter should not be
read when it is enabled.
I
The Compare output is the primary output and the Termi-
nal Count is the auxiliary output (opposite of the Timer).
I
Terminal Count output is full cycle only.
I
When the Counter is disabled and a period value is written
into DR1, the period value is also loaded into DR0. When
the Counter is enabled, the counter counts down until termi-
nal count (a count of 00h) is reached. On the next clock
edge, the period is reloaded and, on subsequent clocks,
counting continues.
The Counter implements a compare function between DR0
and DR2. The Compare signal is the primary function out-
put. Mode bit 1 sets the compare type (DR0 <= DR2 or DR0
< DR2) and Mode bit 0 sets the interrupt type (Terminal
Count or Compare).
The data input functions as a gate to counter operation. The
counter will only count and reload when the data input is
asserted (logic '1'). When the data input is negated (logic
'0'), counting (including the period reload) is halted.
Counters may be chained in 8-bit blocks up to 32 bits.
17.1.6.1
Usability Exceptions
The following are usability exceptions for the Counter func-
tion.
1.
DR0 may only be read (to transfer DR0 data to DR2)
when the block is disabled.
17.1.6.2
Block Interrupt
The Counter block has a selection of three interrupt
sources. Interrupt on Terminal Count and Compare may be
selected in Mode bit 0 of the Function register.
Interrupt on Terminal Count: The positive edge of Termi-
nal Count (auxiliary output) generates an interrupt for
this block. The timing of the interrupt follows the TC
Pulse Width setting in the Control register.
I
Interrupt on Compare: The positive edge of Compare
(primary output) generates an interrupt for this block.
I
相關(guān)PDF資料 |
PDF描述 |
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| CY8C22213-24PVI | PSoC Mixed Signal Array |
| CY8C22213-24SI | PSoC Mixed Signal Array |
| CY8C22213-24SIT | PSoC Mixed Signal Array |
| CY8C24794-SPAX | PSoCTM Mixed-Signal Array |
| CY8C24794-SPE | PSoCTM Mixed-Signal Array |
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| CY8C22213-24PVI | 功能描述:IC MCU 2K FLASH 256B 20-SSOP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C22xxx 標(biāo)準(zhǔn)包裝:60 系列:BlueStreak ; LH7 核心處理器:ARM7 芯體尺寸:32-位 速度:84MHz 連通性:EBI/EMI，SPI，SSI，SSP，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):76 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類型:ROMless EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 |
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| CY8C22345 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC Programmable System-on-Chip |
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