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| 型號(hào)： | CY8C22213-24LFI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | PSoC Mixed Signal Array |
| 中文描述： | MULTIFUNCTION PERIPHERAL, QCC32 |
| 封裝： | 5 X 5 MM, MLF-32 |
| 文件頁(yè)數(shù)： | 268/304頁(yè) |
| 文件大小： | 2956K |
| 代理商： | CY8C22213-24LFI |
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26. I2C
CY8C22xxx Preliminary Data Sheet
268
Document No. 38-12009 Rev. *D
December 22, 2003
The sequence occurs differently between Master transmitter
and Master receiver. As a transmitter, the contention will
occur on a data bit. On the subsequent Byte Complete inter-
rupt, the Lost Arbitration status will be set. In receiver mode,
the contention will occur on the ACK bit. The Master that
NACKed the last reception will lose the arbitration. However,
the hardware will shift in the next byte in response to the
winning Master’s ACK, so that a subsequent Byte Complete
interrupt occurs. At this point, the losing Master can read the
Lost Arbitration status. Contention is checked only at the
eight data bit sampling points and one ACK bit sampling
point.
Bit 5: Stop Status.
Stop status is set on detection of an I2C
Stop condition. This bit is sticky, which means that it will
remain set until a ‘0’ is written back to it by the firmware.
This bit may only be cleared if Byte Complete status is set. If
the Stop Interrupt Enable bit is set, an interrupt will also be
generated on Stop detection. It is never automatically
cleared.
Using this bit, a Slave can distinguish between a previous
Stop or Restart on a given address byte interrupt. In Master
mode, this bit may be used in conjunction with the Stop IE
bit, to generate an interrupt when the bus is free. However,
in this case, the bit must have previously been cleared prior
to the reception of the Stop, in order to cause an interrupt.
Bit 4: ACK.
This control bit defines the acknowledge data
bit that will be transmitted out in response to a received
byte. When receiving, a Byte Complete interrupt is gener-
ated after the eighth data bit is received. On the subsequent
write to this register to continue (or terminate) the transfer,
the state of this bit will determine the next bit of data that will
be transmitted. It is active high. A ‘1’ will send an ACK and a
‘0’ will send a NACK.
A Master Receiver normally terminates a transfer, by writing
a ‘0’ (NACK) to this bit. This releases the bus and automati-
cally generates a Stop condition. A Slave Receiver may also
send a NACK, to inform the Master that it cannot receive
any more bytes.
Bit 3: Address.
This bit is set when an address has been
received. This consists of a Start or Restart, and an address
byte. This bit applies to both master and slave.
In Slave mode, when this status is set, firmware will read the
received address from the data register and compare it with
its own address. If the address does not match, the firmware
will write a NACK indication to this register. No further inter-
rupts will occur, until the next Address is received. If the
address does match, firmware must ACK the received byte,
then Byte Complete interrupts will be generated on subse-
quent bytes of the transfer.
This bit will also be set when address transmission is com-
plete in Master mode. If a lost arbitration occurs during the
transmission of a Master address, indicated by the Lost Arb
bit, the block will revert to Slave mode if enabled. This bit
then signifies that the block is being addressed as a slave.
If Slave mode is not enabled, the Byte Complete interrupt
will still occur to inform the Master of Lost Arbitration.
Bit 2: Transmit.
This bit sets the direction of the shifter for
a subsequent byte transfer. The shifter is always shifting in
data from the I2C bus, but a write of ‘1’ enables the output of
the shifter to drive the SDA output line. Since a write to this
register initiates the next transfer, data must be written to the
data register prior to writing this bit. In Receive mode, the
previously received data must have been read from the data
register before this write. In Slave mode, firmware derives
this direction from the R/W bit in the received slave address.
In Master mode, the firmware decides on the direction and
sets it accordingly.
This direction control is only valid for data transfers. The
direction of address bytes is determined by the hardware,
depending on the Master or Slave mode.
The Master Transmitter terminates a transfer by writing a
zero to the transmit bit. This releases the bus and automati-
cally sends a Stop condition, or a Stop/Start or Restart,
depending on the I2C_MSCR control bits.
Bit 1: LRB (Last Received Bit).
This is the last received
bit in response to a previously transmitted byte. In Transmit
mode, the hardware will send a byte from the data register
and clock in an acknowledge bit from the receiver. On the
subsequent byte complete interrupt, firmware will check the
value of this bit. A ‘0’ is the ACK value and a ‘1’ is a NACK
value. The meaning of the LRB depends on the current
operating mode.
Master Transmitter:
‘0’: ACK, the Slave has accepted the previous byte. The
Master may send another byte by first writing the byte to the
I2C_DR register and then setting the Transmit bit in the
I2C_SCR register. Optionally, the Master may clear the
transmit bit in the I2C_SCR register. This will automatically
send a Stop. If the Start or Restart bits are set in the
I2C_MSCR register, the Stop may be followed by a Start or
Restart.
‘1’: NACK, the Slave cannot accept any more bytes. A Stop
is automatically generated by the hardware on the subse-
quent write to the I2C_SCR register (regardless of the value
written). However, a Stop/Start or Restart condition may also
be generated, depending on whether firmware has set the
Start or Restart bits in the I2C_MSCR register.
Slave Transmitter:
‘0’: ACK, the Master wants to read another byte. The Slave
should load the next byte into the I2C_DR register and set
the transmit bit in the I2C_SCR register, to continue the
transfer.
‘1’: NACK, the Master is done reading bytes. The Slave will
revert to IDLE state on the subsequent I2C_SCR write
(regardless of the value written).
相關(guān)PDF資料 |
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| CY8C22213-24PI | PSoC Mixed Signal Array |
| CY8C22213-24PVI | PSoC Mixed Signal Array |
| CY8C22213-24SI | PSoC Mixed Signal Array |
| CY8C22213-24SIT | PSoC Mixed Signal Array |
| CY8C24794-SPAX | PSoCTM Mixed-Signal Array |
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