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| 型號(hào)： | CY8C22113-24SI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | PSoC Mixed Signal Array |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PDSO8 |
| 封裝： | 0.150 INCH, MS-012, SOIC-8 |
| 文件頁(yè)數(shù)： | 218/304頁(yè) |
| 文件大?。?/td> | 2956K |
| 代理商： | CY8C22113-24SI |
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17. Digital Blocks
CY8C22xxx Preliminary Data Sheet
218
Document No. 38-12009 Rev. *D
December 22, 2003
This resynchronization process (forcing the state back to
idle) occurs regardless of the value of the STOP bit sample.
It is important to reset as soon as possible, so that maximum
performance can be achieved.
Figure 17-28
shows an
example where the RX block clock bit rate is slower than the
external TX bit rate. The sample point shifts to successively
later times. In the extreme case shown, the RX samples the
STOP bit at the trailing edge. In this case, the receiver has
counted 9.5 bit times, while the transmitter has counted 10
bit times. Therefore, for a 10-bit message, the maximum
theoretical clock offset for the message to be received cor-
rectly is represented by one-half bit time, or 5%. If the RX
and TX clocks exceed this offset, a logic '0' may be sampled
for the STOP bit. In this case, the Framing Error status is
set.
Figure 17-28. Example RX Re-Synchronization
This theoretical maximum will be degraded by the resyn-
chronization time, which is fixed at approximately 42 ns. In
a typical 115.2 Kbaud example, the bit time is 8.70 us. In this
case the new maximum offset is:
((4.35 us - 42 ns)/4.35 us) x 5% or 4.95%
At slower baud rates, this value gets closer to the theoretical
maximum of 5%.
Status Generation.
There are five status bits in a Receiver
block: RX Reg Full, RX Active, Framing Error, Overrun, and
Parity Error. All status bits, except RX Active and Overrun,
are set synchronously on the STOP bit sample point.
RX Reg Full
indicates a byte has been received and trans-
ferred into the RX Buffer Register. This status bit is cleared
when the user reads the RX Buffer Register (DR2). The set-
ting of this bit is synchronized to the STOP sample point.
This is the earliest point at which the framing error status
can be set and therefore error status is defined to be valid
when RX Reg Full is set.
RX Active
can be polled to determine if a reception is in
progress. This bit is set on START detection and cleared on
STOP detection. This bit is not sticky and there is no way for
the user to clear it.
Framing Error
status indicates that the STOP bit associ-
ated with a given byte was not received correctly (expecting
a '1', but got a '0'). This will typically occur when the differ-
ence between the baud rates of the transmitter and receiver
is greater than the maximum allowed.
Overrun
occurs when there is a received data byte in the
RX Buffer register and a new byte is loaded into the RX
Buffer register before the user has had a chance to read the
previous one. Because the RX Buffer register is actually a
latch, Overrun status is set one-half cycle before RX Reg
Full. This means that although the new data is not available,
the previous data has been overwritten because the latch
was opened.
Parity Error
status indicates that resulting parity calculation
on the received byte does not match the value of the parity
bit that was transmitted. This status is set on the sample
point of the STOP signal.
Status Clear On Read.
Refer to the SPIM subsection in
“SPIM Timing” on page 209
.
Figure 17-29. Status Timing for Receiver
Start
1
1
0
1
0
0
1
0
1
RXD
Stop
Start
RX clock is slower than TX clock.
Stop Bit is just
recognized.
Need to re-sync
as soon as
possible.
Any delay in
re-sync will cut
into the optimal
sync of the next
byte.
Sample points are
successively later
in the bit times.
CCLK
IDLE
START
BIT0
STATE
BIT1
BIT5
BIT6
BIT7
STOP
RXD
D0
D6
D7
D1
RX_REG_FULL
PARITY_ERROR, FRAMING_ERROR
RX_ACTIVE
IDLE
All status except Overrun is
set synchronously with the
STOP bit sample point.
OVERRUN
Overrun is set cycle
before RX REG Full.
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