參數(shù)資料
型號: CY8C20434
廠商: Cypress Semiconductor Corp.
英文描述: PSoC Mixed-Signal Array(PSoC混合信號陣列)
中文描述: PSoC混合信號陣列(的PSoC混合信號陣列)
文件頁數(shù): 8/32頁
文件大?。?/td> 378K
代理商: CY8C20434
September 18, 2006
Document No. 001-05356 Rev. *B
8
CY8C20234, CY8C20334, CY8C20434 Final Data Sheet
1. Pin Information
1.1.2
24-Pin Part Pinout
Table 1-2. 24-Pin Part Pinout (QFN**)
Pin
No.
Type
Name
Description
CY8C20334 24-Pin PSoC Device
Digital
IO
IO
IO
IOH
IOH
IOH
IOH
Analog
I
I
I
I
I
I
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
P1[1]
NC
Vss
P1[0]
P1[2]
P1[4]
P1[6]
XRES
I2C SCL, SPI SS.
I2C SDA, SPI MISO.
SPI CLK.
CLK*, I2C SCL, SPI MOSI.
No connection.
Ground connection.
DATA*, I2C SDA.
Power
IOH
IOH
IOH
IOH
I
I
I
I
Optional external clock input (EXTCLK).
Input
Active high external reset with internal
pull down.
15
16
17
18
19
20
21
22
23
24
CP
IO
IO
IO
IO
IO
I
I
I
I
I
P2[0]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
P0[7]
P0[5]
P0[3]
P0[1]
Vss
Analog bypass.
Supply voltage.
Power
IO
IO
IO
IO
I
I
I
I
Integrating input.
Power
Center pad must be connected to
ground.
LEGEND
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the
PSoC Mixed-Signal Array Technical Reference Manual
for details.
** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
should be electrically floated and not connected to any other signal.
QFN
(Top View)
AI, P2[5]
AI, P2[3]
AI, P2[1]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
1
2
3
4
5
6
18
17
16
15
14
13
P0[2], AI
P0[0], AI
P2[0], AI
2
2
2
2
2
1
P
P
P
V
P0[4], AI
7
8
9
1
1
1
S
A
A
N
P1[6], AI
A
XRES
P
A
P
V
相關PDF資料
PDF描述
CY8C20234 PSoC Mixed-Signal Array(PSoC混合信號陣列)
CY8C20334 PSoC Mixed-Signal Array(PSoC混合信號陣列)
CY8C22213-24PVIT PSoC Mixed Signal Array
CY8C22113 PSoC Mixed Signal Array
CY8C22113-24PI PSoC Mixed Signal Array
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CY8C20434-12LQXIKA 制造商:Cypress Semiconductor 功能描述: