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參數(shù)資料
| 型號： | CY7C68014A-128AXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Light Pipe; Mounting Hole Dia:3.5mm; Material:Polycarbonate; Length:11.4mm; Color:Clear; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | 8-BIT, EEPROM, 48 MHz, MICROCONTROLLER, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-128 |
| 文件頁數(shù)： | 47/55頁 |
| 文件大?。?/td> | 1958K |
| 代理商： | CY7C68014A-128AXC |
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CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Document #: 38-08032 Rev. *G
Page 47 of 55
9.16
Sequence Diagram
9.16.1
Single and Burst Synchronous Read Example
Figure 9-16
shows the timing relationship of the SLAVE FIFO
signals during a synchronous FIFO read using IFCLK as the
synchronizing clock. The diagram illustrates a single read
followed by a burst read.
At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications).
Note:
t
SFA
has a minimum of 25 ns. This means when IFCLK
is running at 48 MHz, the FIFO address set-up time is more
than one IFCLK cycle.
At = 1, SLOE is asserted. SLOE is an output enable only,
whose sole function is to drive the data bus. The data that
is driven on the bus is the data that the internal FIFO pointer
is currently pointing to. In this example it is the first data
value in the FIFO. Note: the data is pre-fetched and is driven
on the bus when SLOE is asserted.
At t = 2, SLRD is asserted. SLRD must meet the set-up time
of t
SRD
(time from asserting the SLRD signal to the rising
edge of the IFCLK) and maintain a minimum hold time of
t
RDH
(time from the IFCLK edge to the deassertion of the
SLRD signal). If the SLCS signal is used, it must be asserted
with SLRD, or before SLRD is asserted (i.e., the SLCS and
SLRD signals must both be asserted to start a valid read
condition).
The FIFO pointer is updated on the rising edge of the IFCLK,
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of t
XFD
(measured from the rising edge
of IFCLK) the new data value is present. N is the first data
value read from the FIFO. In order to have data on the FIFO
data bus, SLOE MUST also be asserted.
The same sequence of events are shown for a burst read and
are marked with the time indicators of T = 0 through 5.
Note:
For the burst mode, the SLRD and SLOE are left asserted
during the entire duration of the read. In the burst read mode,
when SLOE is asserted, data indexed by the FIFO pointer is
on the data bus. During the first read cycle, on the rising edge
of the clock the FIFO pointer is updated and increments to
point to address N+1. For each subsequent rising edge of
IFCLK, while the SLRD is asserted, the FIFO pointer is incre-
mented and the next data value is placed on the data bus.
IFCLK
SLRD
FLAGS
SLOE
DATA
Figure 9-16. Slave FIFO Synchronous Read Sequence and Timing Diagram
t
SRD
t
RDH
t
OEon
t
XFD
t
XFLG
t
IFCLK
N+1
Data Driven: N
>= t
SRD
t
OEon
t
XFD
N+2
t
XFD
t
XFD
>= t
RDH
t
OEoff
N+4
N+3
t
OEoff
t
SFA
t
FAH
FIFOADR
SLCS
t=0
N+1
t=1
t=2
t=3
t=4
t
FAH
T=0
t
SFA
T=1
T=2
T=3
T=4
N
N
N+1
N+2
FIFO POINTER
N+3
FIFO DATA BUS
N+4
Not Driven
Driven: N
SLOE
SLRD
N+1
N+2
N+3
Not Driven
SLRD
SLOE
IFCLK
Figure 9-17. Slave FIFO Synchronous Sequence of Events Diagram
IFCLK
IFCLK
N+1
IFCLK
IFCLK
N+4
N+4
IFCLK
IFCLK
IFCLK
IFCLK
N+1
SLRD
SLRD
N+1
SLOE
Not Driven
N+4
N+4
IFCLK
SLOE
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| CY7C68014A-56BAXC | 功能描述:8位微控制器 -MCU EZ USB FX2LP Battery PWR LO COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C68014A-56LFXC | 功能描述:8位微控制器 -MCU EZ USB FX2LP Battery Apps LO COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C68014A-56LTXC | 功能描述:8位微控制器 -MCU USB HS Controller RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C68014A-56PVXC | 功能描述:8位微控制器 -MCU EZ USB FX2LP Battery Apps LO COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C68014A-BAXC | 制造商:Cypress Semiconductor 功能描述:MCU 8BIT CISC ROMLESS 3.3V 100TQFP - Trays |
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