參數(shù)資料
型號(hào)： CY7C68013
廠商： Cypress Semiconductor Corp.
英文描述： Universal Serial Bus Microcontroller(EZ-USB FX2 USB 高速USB外圍微控制器)
中文描述： 通用串行總線控制器（的EZ - USB FX2的的USB高速的USB外圍微控制器）
文件頁數(shù)： 13/45頁
文件大?。?/td> 342K
代理商： CY7C68013
CY7C68013
PRELIMINARY
13
3.10.6
Default High-Speed Alternate Settings
NOTE:
“
0
”
means
“
not implemented
”
NOTE:
“
2x
”
means
“
double buffered
”
*Note: Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer
packets larger than 64 bytes to EP1.
3.11
External FIFO interface
3.11.1
The FX2 slave FIFO architecture has eight 512-byte blocks in the endpoint RAM which directly serve as FIFO memories, and are
controlled by FIFO control signals (such as IFCLK, SLRD, SLWR, SLOE, PKTEND, and flags).
In operation, some of the eight RAM blocks fill or empty from the SIE, while the others are connected to the I/O transfer logic.
The transfer logic takes two forms, the GPIF for internally generated control signals, or the slave FIFO interface for externally
controlled transfers.
Architecture
3.11.2
The FX2 endpoint FIFOS are implemented as eight physically distinct 256x16 RAM blocks. The 8051/SIE can switch any of the
RAM blocks between two domains, the USB(SIE) domain and the 8051-I/O Unit domain. This switching is done virtually instan-
taneously, giving essentially zero transfer time between
“
USB FIFOS
”
and
“
Slave FIFOS.
”
Since they are physically the same
memory, no bytes are actually transferred between buffers.
At any given time, some RAM blocks are filling/emptying with USB data under SIE control, while other RAM blocks are available
to the 8051 and/or the I/O control unit. The RAM blocks operate as single-port in the USB domain, and dual-port in the 8051-I/O
domain. The blocks can be configured as single, double, triple, or quad buffered as previously shown.
The I/O control unit implements either an internal-master (M for master) or external-master (S for Slave) interface.
In Master (M) mode, the GPIF internally controls FIFOADR[1..0] to select a FIFO. The RDY pins (two in the 56-pin package, six
in the 100-pin and 128-pin packages) can be used as flag inputs from an external FIFO or other logic if desired. The GPIF can
be run from either an internally derived clock or externally supplied clock (IFCLK), at a rate that transfers data up to 96 Mega-
bytes/s (48 MHz).
In Slave (S) mode, the FX2 accepts either an internally derived clock or externally supplied clock (IFCLK, max. frequency 48
MHz) and SLRD, SLWR, SLOE, PKTEND signals from external logic. Each endpoint can individually be selected for byte or word
operation by an internal configuration bit, and a Slave FIFO Output Enable signal SLOE enables data of the selected width.
External logic must insure that the output enable signal is inactive when writing data to a slave FIFO. The slave interface can also
operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in synchronous
mode.
Master/Slave Control Signals
3.11.3
An 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 MHz and 48 MHz. Alternatively,
an externally supplied clock, of up to 48 MHz, feeding the IFCLK pin can be used as the interface clock. IFCLK can be configured
to function as an output clock when the GPIF and FIFOs are internally clocked. An output enable bit in the IFCONFIG register
turns this clock output off, if desired.
GPIF and FIFO clock rates
Table 3-3. Default High-Speed Alternate Settings
Alternate Setting
ep0
0
64
1
2
3
64
64
64
ep1out
0
512 bulk*
64 int
64 int
ep1in
0
512 bulk*
64 int
64 int
ep2
0
512 bulk out (2x)
512 int out (2x)
512 iso out (2x)
ep4
0
512 bulk out (2x)
512 bulk out (2x)
512 bulk out (2x)
ep6
0
512 bulk in (2x)
512 int in (2x)
512 iso in (2x)
ep8
0
512 bulk in (2x)
512 bulk in (2x)
512 bulk in (2x)
相關(guān)PDF資料
PDF描述
CY7C68015A EZ-USB FX2LP USB Microcontroller
CY7C68013A-100AXC Hook-Up Wire; Conductor Size AWG:26; No. Strands x Strand Size:7 x 34; Jacket Color:Purple; Approval Bodies:UL, CSA; Approval Categories:UL AWM Styles 1007, 1565; CSA Types TR-64, TRSR-64; JQA-F; Passes VW-1 Flame Test RoHS Compliant: Yes
CY7C68014A-100AXC Light Pipe; Mounting Hole Dia:3.5mm; Material:Polycarbonate; Length:10.2mm; Color:Clear; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes
CY7C68014A-128AXC Light Pipe; Mounting Hole Dia:3.5mm; Material:Polycarbonate; Length:11.4mm; Color:Clear; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes
CY7C68014A EZ-USB FX2LP USB Microcontroller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C68013-100AC 功能描述:IC MCU USB PERIPH HI SPD 100LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:EZ-USB FX2LP™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲(chǔ)器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382
CY7C68013-100AXC 功能描述:IC MCU USB PERIPH HI SPD 100LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:EZ-USB FX2LP™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲(chǔ)器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382
CY7C68013-128AC 制造商:Cypress Semiconductor 功能描述:MCU 8-bit FX2LP 8051 CISC ROMLess 3.3V 128-Pin TQFP
CY7C68013-56LFC 制造商:Cypress Semiconductor 功能描述:MCU 8-bit FX2LP 8051 CISC ROMLess 3.3V 56-Pin QFN EP
CY7C68013-56LFXC 制造商:Cypress Semiconductor 功能描述:MCU 8-Bit FX2LP 8051 CISC ROMLess 3.3V 56-Pin QFN EP
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