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參數(shù)資料
| 型號： | CY7C64013 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Full-Speed USB (12 Mbps) Function(全速 USB (12 Mbps)性能) |
| 中文描述： | 全速USB（12 Mbps）的功能（全速的USB（12 Mbps）的性能） |
| 文件頁數(shù)： | 16/46頁 |
| 文件大?。?/td> | 381K |
| 代理商： | CY7C64013 |
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CY7C64013
CY7C64113
PRELIMINARY
16
7.0
Reset
The CY7C64x13 supports two resets: Power-On Reset (POR) and a Watch Dog Reset (WDR). Each of these resets causes:
all registers to be restored to their default states,
the USB Device Address to be set to 0,
all interrupts to be disabled,
the PSP and Data Stack Pointer (DSP) to be set to memory address 0x00.
The occurrence of a reset is recorded in the Processor Status and Control Register, as described in Section 15.0. Bits 4 and 6
are used to record the occurrence of POR and WDR, respectively. Firmware can interrogate these bits to determine the cause
of a reset.
Program execution starts at ROM address 0x0000 after a reset. Although this looks like interrupt vector 0, there is an important
difference. Reset processing does NOT push the program counter, carry flag, and zero flag onto program stack. The firmware
reset handler should configure the hardware before the
“
main
”
loop of code. Attempting to execute a RET or RETI in the firmware
reset handler causes unpredictable execution results.
7.1
When V
CC
is first applied to the chip, the Power-On Reset (POR) signal is asserted and the CY7C64x13 enters a
“
semi-suspend
”
state. During the semi-suspend state, which is different from the suspend state defined in the USB specification, the oscillator
and all other blocks of the part are functional, except for the CPU. This semi-suspend time ensures that both a valid V
CC
level is
reached and that the internal PLL has time to stabilize before full operation begins. When the V
CC
has risen above approximately
2.5V, and the oscillator is stable, the POR is deasserted and the on-chip timer starts counting. The first 1 ms of suspend time is
not interruptible, and the semi-suspend state continues for an additional 95 ms unless the count is bypassed by a USB Bus Reset
on the upstream port. The 95 ms provides time for V
CC
to stabilize at a valid operating voltage before the chip executes code.
If a USB Bus Reset occurs on the upstream port during the 95-ms semi-suspend time, the semi-suspend state is aborted and
program execution begins immediately from address 0x0000. In this case, the Bus Reset interrupt is pending but not serviced
until firmware sets the USB Bus Reset Interrupt Enable bit (bit 0 of register 0x20) and enables interrupts with the EI command.
The POR signal is asserted whenever V
CC
drops below approximately 2.5V, and remains asserted until V
CC
rises above this level
again. Behavior is the same as described above.
Power-On Reset (POR)
7.2
The Watch Dog Timer Reset (WDR) occurs when the internal Watch Dog timer rolls over. Writing any value to the write-only
Watch Dog Restart Register at address 0x26 clears the timer. The timer rolls over and WDR occurs if it is not cleared within
t
WATCH
(8 ms minimum) of the last clear. Bit 6 of the Processor Status and Control Register is set to record this event (the register
contents are set to 010X0001 by the WDR). A Watch Dog Timer Reset lasts for 2 ms, after which the microcontroller begins
execution at ROM address 0x0000.
Watch Dog Reset (WDR)
Figure 7-1. Watch Dog Reset (WDR)
The USB transmitter is disabled by a Watch Dog Reset because the USB Device Address Register is cleared (see Section 18.1).
Otherwise, the USB Controller would respond to all address 0 transactions.
It is possible for the WDR bit of the Processor Status and Control Register (0xFF) to be set following a POR event. The WDR bit
should be ignored If the firmware interrogates the Processor Status and Control Register for a Set condition on the WDR bit and
if the POR (bit 3 of register 0xFF) bit is set.
Last write to
Watch Dog Timer
Register
No write to WDT
register, so WDR
goes HIGH
Execution begins at
Reset Vector 0x0000
t
WATCH
2 ms
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C64013A-PXC | 功能描述:IC MCU 8K FULL SPEED USB 28SDIP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:M8™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C64013A-SXC | 功能描述:IC MCU 8K FULL SPEED USB 28SOIC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:M8™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C64013C-PXC | 功能描述:IC MCU 8K FULL SPEED USB 28DIP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:M8™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C64013C-SXC | 功能描述:8位微控制器 -MCU Full Spd USB 12-Mbps Function RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C64013C-SXCT | 功能描述:8位微控制器 -MCU Full Spd USB 12-Mbps Function RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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