參數(shù)資料
型號: CY7C63813
廠商: Cypress Semiconductor Corp.
英文描述: enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設控制器)
中文描述: enCoRe II還低速USB外設控制器(enCoRe II還低速的USB外設控制器)
文件頁數(shù): 43/74頁
文件大小: 1441K
代理商: CY7C63813
CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 43 of 74
Table 16-12. Capture Interrupt Enable (TCAPINTE) [0x2B] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
Cap1 Fall
Enable
Cap1 Rise
Enable
Cap0 Fall
Enable
Cap0 Rise
Enable
Read/Write
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit [7:4]:
Reserved
Bit 3:
Cap1 Fall Enable
0 = Disable the capture 1 falling edge interrupt
1 = Enable the capture 1 falling edge interrupt
Bit 2:
Cap1 Rise Enable
0 = Disable the capture 1 rising edge interrupt
1 = Enable the capture 1 rising edge interrupt
Bit 1:
Cap0 Fall Enable
0 = Disable the capture 0 falling edge interrupt
1 = Enable the capture 0 falling edge interrupt
Bit 0:
Cap0 Rise Enable
0 = Disable the capture 0 rising edge interrupt
1 = Enable the capture 0 rising edge interrupt
Table 16-13. Capture Interrupt Status (TCAPINTS) [0x2C] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
Cap1 Fall
Active
Cap1 Rise
Active
Cap0 Fall
Active
Cap0 Rise
Active
Read/Write
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit [7:4]:
Reserved
Bit 3:
Cap1 Fall Active
0 = No event
1 = A falling edge has occurred on Cap1
Bit 2:
Cap1 Rise Active
0 = No event
1 = A rising edge has occurred on Cap1
Bit 1:
Cap0 Fall Active
0 = No event
1 = A falling edge has occurred on Cap0
Bit 0:
Cap0 Rise Active
0 = No event
1 = A rising edge has occurred on Cap0
Note:
The interrupt status bits must be cleared by firmware to enable subsequent interrupts. This is achieved by writing a ‘1’ to
the corresponding Interrupt status bit.
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