參數(shù)資料
型號(hào): CY7C63743-PC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
中文描述: 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDIP24
封裝: 0.300 INCH, PLASTIC, DIP-24
文件頁(yè)數(shù): 17/58頁(yè)
文件大?。?/td> 1236K
代理商: CY7C63743-PC
FOR
FOR
enCoRe
USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 17 of 58
and trips BOR, the part remains in reset until V
CC
rises above V
LVR
. At that point, the t
START
delay occurs before normal operation
resumes, and the microcontroller starts executing code from address 0x00 after the t
START
delay.
In suspend mode, only the BOR detection is active, giving a reset if V
CC
drops below approximately 2.5V. Since the device is
suspended and code is not executing, this lower reset voltage is safe for retaining the state of all registers and memory. Note that
in suspend mode, LVR is disabled as discussed in Section 10.1.
10.3
The Watchdog Timer Reset (WDR) occurs when the internal Watchdog timer rolls over. Writing any value to the write-only
Watchdog Reset Register at address 0x26 will clear the timer. The timer will roll over and WDR will occur if it is not cleared within
t
WATCH
(see
Figure 10-1
) of the last clear. Bit 6 (Watchdog Reset bit) of the Processor Status and Control Register is set to record
this event (see Section 20.0 for more details). A Watchdog Timer Reset typically lasts for 2–4 ms, after which the microcontroller
begins execution at ROM address 0x0000.
t
WATCH = 10.1 to
Watchdog Reset (WDR)
11.0
Suspend Mode
The CY7C637xx parts support a versatile low-power suspend mode. In suspend mode, only an enabled interrupt or a LOW state
on the D–/SDATA pin will wake the part. Two options are available. For lowest power, all internal circuits can be disabled, so only
an external event will resume operation. Alternatively, a low-power internal wake-up timer can be used to trigger the wake-up
interrupt. This timer is described in Section 11.2, and can be used to periodically poll the system to check for changes, such as
looking for movement in a mouse, while maintaining a low average power.
The CY7C637xx is placed into a low-power state by setting the Suspend bit of the Processor Status and Control Register
(
Figure 20-1
). All logic blocks in the device are turned off except the GPIO interrupt logic, the D–/SDATA pin input receiver, and
(optionally) the wake-up timer. The clock oscillators, as well as the free-running and watchdog timers are shut down. Only the
occurrence of an enabled GPIO interrupt, wake-up interrupt, SPI slave interrupt, or a LOW state on the D–/SDATA pin will wake
the part from suspend (D– LOW indicates non-idle USB activity). Once one of these resuming conditions occurs, clocks will be
restarted and the device returns to full operation after the oscillator is stable and the selected delay period expires. This delay
period is determined by selection of internal vs. external clock, and by the state of the Ext. Clock Resume Delay as explained in
Section 9.0.
In suspend mode, any enabled and pending interrupt will wake the part up. The state of the Interrupt Enable Sense bit (Bit 2,
Figure 20-1
) does not have any effect. As a result, any interrupts not intended for waking from suspend should be disabled through
the Global Interrupt Enable Register and the USB End Point Interrupt Enable Register (Section 21.0).
If a resuming condition exists when the suspend bit is set, the part will still go into suspend and then awake after the appropriate
delay time. The Run bit in the Processor Status and Control Register must be set for the part to resume out of suspend.
Once the clock is stable and the delay time has expired, the microcontroller will execute the instruction following the I/O write that
placed the device into suspend mode before servicing any interrupt requests.
To achieve the lowest possible current during suspend mode, all I/O should be held at either V
CC
or ground
.
In addition, the
GPIO
bit
interrupts (
Figure 21-4
and
Figure 21-5
) should be disabled for any pins that are not being used for a wake-up interrupt. This
should be done even if the main GPIO Interrupt Enable (
Figure 21-1
) is off.
Typical code for entering suspend is shown below:
...
; All GPIO set to low-power state (no floating pins, and bit interrupts disabled unless using for wake-up)
...
; Enable GPIO and/or wake-up timer interrupts if desired for wake-up
...
; Select clock mode for wake-up (see Section 11.1)
mov a, 09h
; Set suspend and run bits
iowr FFh
; Write to Status and Control Register - Enter suspend, wait for GPIO / wake-up interrupt or USB activity
nop
; This executes before any ISR
...
; Remaining code for exiting suspend routine
At least 10.1 ms
since last write to WDR
WDR goes HIGH
for 2–4 ms
Execution begins at
ROM Address 0x0000
2–4 ms
14.6 ms
(at F
OSC
= 6 MHz)
WDR
Figure 10-1. Watchdog Reset (WDR, Address 0x26)
相關(guān)PDF資料
PDF描述
CY7C63743C enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器)
CY7C63723C enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器)
CY7C63803 enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
CY7C63310 enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
CY7C63801 enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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