參數(shù)資料
型號: CY7C63723-SC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
中文描述: 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO18
封裝: 0.300 INCH, PLASTIC, MO-119, SOIC-18
文件頁數(shù): 41/58頁
文件大?。?/td> 1236K
代理商: CY7C63723-SC
FOR
FOR
enCoRe
USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 41 of 58
The polarity that triggers an interrupt is controlled independently for each GPIO pin by the GPIO Interrupt Polarity Registers.
Figure 21-6
and
Figure 21-7
control the interrupt polarity of each GPIO pin.
Bit [7:0]: P0[7:0] Interrupt Polarity
1 = Rising GPIO edge
0 = Falling GPIO edge
Bit [7:0]: P1[7:0] Interrupt Polarity
1 = Rising GPIO edge
0 = Falling GPIO edge
Bit #
7
6
5
4
3
2
1
0
Bit Name
P0 Interrupt Polarity
Read/Write
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
Figure 21-6. Port 0 Interrupt Polarity Register (Address 0x06)
Bit #
7
6
5
4
3
2
1
0
Bit Name
P1 Interrupt Polarity
Read/Write
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
Figure 21-7. Port 1 Interrupt Polarity Register (Address 0x07)
Figure 21-8. GPIO Interrupt Diagram
Port Bit Interrupt
Polarity Register
OR Gate
(1 input per
GPIO pin)
GPIO Interrupt
Flip Flop
CLR
GPIO
Pin
1 = Enable
0 = Disable
Port Bit Interrupt
Enable Register
1 = Enable
0 = Disable
Interrupt
Priority
Encoder
IRQout
Interrupt
Vector
D
Q
M
U
X
1
Global
GPIO Interrupt
Enable
(Bit 6, Register 0x20)
IRA
相關PDF資料
PDF描述
CY7C63743-SC enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63722 enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63723 enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63723-PC enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63743 enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
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